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Open source CMOS reusable blocks for LTspice IV and Magic 8 
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In January 2015 I was playing with LTspice IV and decided to create a number of reusable blocks of CMOS logic for our nedoPC.org community, my NEDOCON company and anybody interested.
Later I added CMOS layouts, created in Magic VLSI Layout Tool v8.0, and some were even silicon proven in October 2015 for CMOS 0.5um technology...

http://nedopc.io/nedopc/files/nedocon-cmoslib.zip (693K) v1.0alpha (March 2016)

This PUBLIC DOMAIN archive consists of a number of close to reality
CMOS blocks for LTspice IV in form of ASC and ASY files that you need
to copy (from "sym" subfolder) to

C:\Program Files\LTC\LTspiceIV\lib\sym\

You can see internals of any block and you can use it anywhere.
Tests are also included with screenshots of oscillograms. Enjoy!

cmos-not - NOT gate (invertor)
cmos-nand - 2-input NOT-AND gate
cmos-nand3 - 3-input NOT-AND gate
cmos-nor - 2-input NOT-OR gate
cmos-nor3 - 3-input NOT-OR gate
cmos-tgate - transmission gate (SPST switch)
cmos-tgate2 - 2 transmission gates connected as SPDT switch

Then it will be xor, nor-and, rs-trig, d-trig, mux2, mux4, mux8 etc.

P.S. Used book:

Uyemura, John P. Circuit design for CMOS VLSI. 1992 (11th printing 1998) ISBN 0-7923-9184-5

P.P.S. On January 8th, 2016 I started adding silicon proven Magic layouts here...

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Last edited by Shaos on 16 Feb 2015 04:05, edited 14 times in total.



24 Jan 2015 20:41
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Inverter cmos-not (with added parasitic capacitor on output to simulate gate delay - about 0.1ns):



Testing:



Voltage transfer curve:

Image

P.S. In January 2016 CMOS layout 0.5um for Magic v8.0 was added here (silicon proven in October 2015):



Simulation of 1 GHz input (SPICE model extracted from layout by Magic and simulated by ngspice):


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Last edited by Shaos on 04 Feb 2015 10:32, edited 2 times in total.



24 Jan 2015 21:18
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Two input NAND block cmos-nand (with parasitic capacitor on output to simulate gate delay - about 0.2ns):



Test schematics:



Voltage transfer curve:

Image

Blue curve is output when both inputs connected together and two other curves for cases when one of the inputs tied to high voltage.

P.S. Magic layout and simulation (silicon proven in October 2015):



Both inputs changed, then just one - 1st one (A) and 2nd one (B):


1GHz signal on both inputs:

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Last edited by Shaos on 07 Feb 2015 07:26, edited 4 times in total.



24 Jan 2015 21:21
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Two input NOR cmos-nor



Test schematics:



Voltage transfer curve:

Image

Blue curve is output when both inputs connected together and two other curves for cases when one of the inputs tied to the ground.

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Last edited by Shaos on 07 Feb 2015 07:27, edited 2 times in total.



24 Jan 2015 21:24
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Single CMOS switch (transmission gate) cmos-tgate




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Last edited by Shaos on 30 Jan 2015 22:51, edited 1 time in total.



25 Jan 2015 02:14
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SPDT CMOS-switch (2 transmission gates) cmos-tgate2




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Last edited by Shaos on 30 Jan 2015 22:52, edited 1 time in total.



25 Jan 2015 02:55
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Three input NAND block cmos-nand3



Test schematics:



Voltage transfer curve:

Image

Curve is moving if we connect different number of inputs to V+

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14 Feb 2015 19:14
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Post 
Three input NOR block cmos-nor3



Test schematics:



Voltage transfer curve:

Image

Curve is moving if connect different number of inputs to ground

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14 Feb 2015 19:16
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I moved library elements to folder "sym"

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07 Jun 2015 00:18
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I decided to add "silicon proven" layouts of CMOS reusable blocks to the same archive...

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06 Jan 2016 17:55
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And now on Hackaday!

https://hackaday.io/project/11779-shared-silicon

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03 Oct 2016 00:20
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