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[Ternary] CMOS Inverter already ternary? 
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Maniac

Joined: 17 Sep 2012 14:36
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I haven't really done any thorough research on the subject, but I was looking over the design of a standard CMOS inverter, and figured that it should in theory be able to invert a ternary signal without any sort of modification.

It sort of depends on either finding a CMOS gate that either has a relatively low tolerance, or can withstand unusually large voltages (twice the usual).

You simply feed it V_dd = V_0, V_ss = -V_0, and then the output voltage should be as follows:

Code:
V_in  V_out
 V_0   -V_0
  0      0
-V_0    V_0


16 Mar 2009 13:50
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Joined: 09 Jan 2003 00:22
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Yes, it is possible for very old CMOS inverters (that do not have output buffers), but in the middle of voltage you will have big current, because both transistors will be partially ON (check this scheme in any electronics simulation software). Also in the middle that curve has a tendency to shift a little bit, so you probably will never get exactly 0.5Vpp at output if you have 0.5Vpp on input...


16 Mar 2009 17:35
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Maniac

Joined: 17 Sep 2012 14:36
Posts: 277
Location: 81.170.128.52
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You may be right. This transistor stuff is pretty new to me, and I'm learning it backwards. I know all the quantum mechanics on how they work on the inside, but I'm still learning the details about how they practically interact with each other.

I did run a simulation, but I may have gotten it wrong somewhere.


16 Mar 2009 17:51
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10 Nov 2012 09:56
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