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[Ternary] Jay's stuff 
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jay4th sent me some files for publication under GPLv3:

1st is schematics of TRIMUX, but in kind of ladder logic interpretation:

Image

2nd is archive with a number of designs files for ternary latch and adders based on DG403:

http://www.nedopc.org/ternary/jay4th/ja ... -12-06.tgz (31K)

P.S. You need gEDA (gschem and pcb) to see them


08 Dec 2010 19:00
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Shaos wrote:
2nd is archive with a number of designs files for ternary latch and adders based on DG403:

http://www.nedopc.org/ternary/jay4th/ja ... -12-06.tgz (31K)

P.S. You need gEDA (gschem and pcb) to see them


These are exported schematics from that archive (images are clickable):

Level triggered ternary latch:

Image

1-trit full adder:

Image

3-trit ripple carry adder:

Image

P.S. Copyright jay4th under GPLv3


08 Dec 2010 19:04
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I drew this schematic (the very first) as a way to explain my non-standard use of ladder logic symbols to represent DG403 and similar CMOS switches. From lader logic --[ ]-- represents a normally open switch, and --[/]-- a normally closed one. (Goolge btw translates Russian references to 'keys' when I would say 'switch' in English.) Then in place of a ladder logic coil, which we normally think of as an output on a single rung of ladder logic, I moved the coil back under the switches where normal relay schematics would draw it. But I put a + or a 0 to represent that a particular 'coil' is 'energized' when the voltage is in the + level, or in the 0 level (or above).

I think this diagram style is clearer and more concise than the alternative which I used in the first of the next few diagrams.

The actual circuit is exactly the one Shaos presented earlier. If there are differences it is a mistake on my part, not an innovation.


08 Dec 2010 21:44
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The second schematic shows the same design for a D-tri-latch in two ways, with my 'laderish' symbols, and more tradional 'relayish' ones. The third circuit on that diagram is an alternative design for a D-tri-latch. Note: none of these circuits have been built or tested.

The last two schematics are of a one trit, and a three trit (ripple carry) full adder. Nothing is new or special in them, they are very straightforward implementations as just a simple network of MUXes (with 4 optimizations where a MUX computes a function of the form xyy or xxy.)

The tar file includes circuit board layouts for the one trit and the three trit adder, again nothing has been built or tested. Soon... I have a job now sometime soon I'll have money to play with electronics. For now I play with free software. I am most interested in testing/developing the latch designs, would love to hear from folks that experiment with building these or similar circuits.


08 Dec 2010 21:48
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All this stuff is now on my git hub repository:

git://github.com/jay3th/threeth.git
https://github.com/jay3th/threeth
logisim-trinary-simulator.zip (30K)

Also a trinary circuit lab (and eventually computer) 'built' using the (Java based, open source) Logisim simulator. http://ozark.hendrix.edu/~burch/logisim/

Current simulator/lab/project/thingy has the basic gates (TAND (aka min), TOR (aka max), TNAND, TNOR), inverters (STI, NTI, PTI) as well as cycle-up and cycle-down. Also a one trit latch, one trit register, 6 trit register, 6 trit x 18 element stack, and balanced base 9 input/output with a keypad and 7 segment led. Working on a 6 trit counter.

The logisim lab thing is simulating trinary using two bits per trit. What is interesting is that the implementation of all the basic gates is two binary gates or less, usually an AND and an OR gate.

Jay


12 Dec 2010 02:23
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Very interesting!
P.S. Direct link to the ternary library for logisim: https://github.com/jay3th/threeth/raw/m ... lator.circ
P.P.S. Logisim even has documentation in Russian: http://ozark.hendrix.edu/~burch/logisim/ru/docs.html
P.P.P.S. Just saved circuit file here for archiving purposes (see previous post)


12 Dec 2010 06:44
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Thanks for the links, and woot! 6t counter!!

Hmmm... maybe a stack based calculator next... only a few steps from a calculator to a computer after all.


12 Dec 2010 09:02
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jay4th wrote:
Thanks for the links, and woot! 6t counter!!

Hmmm... maybe a stack based calculator next... only a few steps from a calculator to a computer after all.


You are incredibly fast ;)


12 Dec 2010 09:11
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I dunno about fast, probably spent 5 hours on the counter. It has 'issues'. On 'power up' it doesn't have a defined value, so I had to make a "set" interface. Turns out the easiest number to set it to was 111111t, or 444 base 9. It counts up, so the next count takes it to..... lol.... jjjjjjt i.e. 6 -1's in a row. I think it uses too many gates, too complicated, gotta be an easier way. But I'm starting to 'think' trinary logic now. If I keep working on it I could get fast maybe...

Jay


12 Dec 2010 09:28
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Logisim "lab" / library now includes 1:3 decode (asserted -1) and 3:1 MUX. Turns out -1 vs 1 is a nice select/don't select signal. A sum-of-products done with nand's can use -1/1 to select one of the products, which is how the 3:1 mux is implemented.

Jay


13 Dec 2010 03:28
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And now a 1t and 6t (ripple carry) full adder, and a calculator example. The calculator has 3 commands: enter, +, and negate. You need to hold the buttons down for a second or so, I was lazy and didn't make a real clock, the feed back path from the stack through the adder to the stack will "oscilate" if you hit the buttons too quickly.


13 Dec 2010 10:55
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jay4th wrote:
And now a 1t and 6t (ripple carry) full adder, and a calculator example. The calculator has 3 commands: enter, +, and negate. You need to hold the buttons down for a second or so, I was lazy and didn't make a real clock, the feed back path from the stack through the adder to the stack will "oscilate" if you hit the buttons too quickly.


It looks like you will build complete ternary computer before us ;)


13 Dec 2010 21:02
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A simulation of one anyway... But that is my plan in general. Build simulators first to debug and review the design. After it all looks good in the simulator, all the software works, then break out the soldering iron. Each trinary gate (simulation) takes one and and one or gate (usually). So from the statistics, my calculator is about 2000 gates. Though most of that is in the 6t x 18 stack. Very excessive for a calculator, but plenty big enough for a 6t CPU. A real CPU probably will come in at 2x to 3x the size of the calculator. Could save plenty by replacing the 'real' trinary stacks with binary memory.

| STI Simple Ternary Inverter | logisim-trinary-simulator | 0 | 9 | 490 |
| NTI Negative Trinary Inverter | logisim-trinary-simulator | 0 | 1 | 102 |
| PTI Positive Trinary Inverter | logisim-trinary-simulator | 1 | 5 | 486 |
| CU Cycle Up | logisim-trinary-simulator | 12 | 12 | 12 |
| TNAND 3 input | logisim-trinary-simulator | 0 | 1 | 256 |
| TNAND fast, 3 input, unsafe | logisim-trinary-simulator | 0 | 1 | 102 |
| TNAND fast, 2 input, unsafe | logisim-trinary-simulator | 0 | 5 | 818 |
| TNOR fast, 2 input, unsafe | logisim-trinary-simulator | 0 | 1 | 102 |
| TOR (max) 3 input | logisim-trinary-simulator | 1 | 1 | 1 |
| 3:1 MUX | logisim-trinary-simulator | 0 | 20 | 102 |
| D-Latch (level triggered) | logisim-trinary-simulator | 4 | 6 | 256 |
| Register (master-slave D-latch) | logisim-trinary-simulator | 0 | 12 | 126 |
| 1t full adder | logisim-trinary-simulator | 0 | 6 | 6 |
| 6t STI | logisim-trinary-simulator | 1 | 1 | 1 |
| 6t 3:1 MUX | logisim-trinary-simulator | 3 | 3 | 3 |
| 6t Register | logisim-trinary-simulator | 2 | 20 | 20 |
| 6t x 18 stack | logisim-trinary-simulator | 1 | 1 | 1 |
| 6t ripple carry adder | logisim-trinary-simulator | 1 | 1 | 1 |
| 2t-to-7seg driver | logisim-trinary-simulator | 18 | 18 | 18 |
| keyboard input | logisim-trinary-simulator | 1 | 1 | 1 |
| tri-led-driver | logisim-trinary-simulator | 7 | 7 | 7 |
| 0 Constant Trit | logisim-trinary-simulator | 1 | 1 | 1 |
| Splitter | Base | 14 | 53 | 5119 |
| Pin | Base | 0 | 85 | 8349 |
| Probe | Base | 5 | 11 | 11 |
| Label | Base | 0 | 38 | 10233 |
| Constant | Gates | 2 | 7 | 17 |
| AND Gate | Gates | 0 | 5 | 1279 |
| OR Gate | Gates | 9 | 25 | 1902 |
| Multiplexer | Plexers | 0 | 18 | 18 |
| Decoder | Plexers | 0 | 10 | 1378 |
| ROM | Memory | 0 | 1 | 18 |
| Button | Input/Output | 12 | 12 | 12 |
| LED | Input/Output | 21 | 21 | 21 |
| 7-Segment Display | Input/Output | 18 | 18 | 18 |
| TOTAL (without project's subcircuits) | | 81 | 304 | 28375 |
| TOTAL (with subcircuits) | | 134 | 437 | 31287 |


13 Dec 2010 21:35
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I understand now format of circ-files and it should be easy to write a converter from DDT to Logisim (and not so easy one from Logisim to DDT).

P.S. Also I know how to create JAR-libraries for Logisim. So I may do in Java: fast version of ternary multiplexer (MUX), simplified multiplexers (E12 and E21), memory (MEM) and even ternary inputs (ports that display -1/0/+1 or N/O/P instead of 10/00/01) and ternary outputs (-1/0/+1 or N/O/P and RED-GREEN LED).


15 Dec 2010 00:02
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Very cool re. understanding how to make a DDT -> Logisim connection!

Re. making Java libraries for Logisim, it seems to me there are 3 easy things that would have high value.

The highest value is to implement DG403 'gates'. There are two reasons I'll get to the second reason below. The primary reason is then we can simulate trinary computers built from DG403's, and can start getting a real handle on size/speed/cost.

Lower value, but easier and so probably a good place to start, would be 2-rail-2-level (i.e. Binary Coded Trinary) switches and LEDs. A two or three color LED would be nice, a two or three level switch and configurable pushbutton would be really nice too.

I have interesting and closely related news about my logisim trinary simulator. I have minimized the adder a bit, I still suspect smaller implementations exist, but at this point I have a reasonable chip count. If you really implemented the adder using 2-rail-2-level and common binary gates, a 1t full adder would need 17 AND chips, 17 OR chips, and 2 NOT chips. (Actually the counts are 65 AND gates, 65 OR gates, and 12 NOT gates aka inverters.) In other words, a 1t full adder fills a single 100x160mm PCB. This is in contrast to the DG403 implementations which is 12 chips total. So the 2-rail-2-level implementation is about 3x chip count compared to the DG403. The only good news is that the 2-rail-2-level implementation runs faster. A DG403 switch takes about 150ns to operate, the comparable 2-rail-2-level implementation has about 3-6 gate delays, at 5 ns gate delay, and 6 delay implementation figure, we get 30 ns instead of 150, or 5x speed up.

So it is both more 'real' and smaller to implement a trinary computer using DG403's, and so it is even more valuable to get a DG403 Java-library chip into logisim.

There are two interesting implementations: exactly as is (more or less). Due to logisim limitations though you won't be able to change logic levels. So even though the part can do real trinary, in logisim it will be binary. The other interesting implementation is a 2-rail-2-level 'simulation'. Let each switch be 2 bits wide, so the simulated chip would be 2 x DPST NO switches, and 2 DPST NC switches. Then use a split/join to chose what 'logic level' the chip responds to.

Of course Logisim is open source, it's just a matter of programming to make logisim handle multi-value logic in general, and trinary in particular. Anyone looking for a project?

Jay


15 Dec 2010 03:19
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