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[Ternary] Dream chip (trinary PAL/GAL) 
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The odds that any trinary enthusiast could get the money together to fab some chips is low. But what if there was just a single chip we could all agree would be perfect. Maybe the 27 or so enthusiast in the world could afford it together, or make enough of a market. What if there were a trinary PAL/GAL?

I imagine something about the density of a 22V10 or similar PAL. Though maybe FPGA like grid of 9x9, (or bigger) cells would be a better organization than sum-of-products type PAL. Though this falls into the 'if I win the lottery' type of dream, it's not as crazy as some I've had.

Jay


13 Dec 2010 03:53
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jay4th wrote:
The odds that any trinary enthusiast could get the money together to fab some chips is low. But what if there was just a single chip we could all agree would be perfect. Maybe the 27 or so enthusiast in the world could afford it together, or make enough of a market. What if there were a trinary PAL/GAL?

I imagine something about the density of a 22V10 or similar PAL. Though maybe FPGA like grid of 9x9, (or bigger) cells would be a better organization than sum-of-products type PAL. Though this falls into the 'if I win the lottery' type of dream, it's not as crazy as some I've had.

Jay


I just a few weeks ago thought about that. My idea was to involve ternary multiplexers for LUTs and for interconnections plus ternary version of SPI might be used for programming and debugging.


13 Dec 2010 23:01
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Yes I was thinking something like each cell would have a 3 input LUT (27 rows, 1 collumn, 27 trits total). A latch/flip-flop/trigger and an optional feed back path. The three input come from fixed sides, the one output to a fixed side? Or to one of 3 sides?? Keep it simple though.

Then the pins should be able to map to many more than one of the cells. Assuming a 16 pin dip, you should be able to build anything from a 12 input 0 output, 11 input 1 output, ... to 0 input 12 output chip. Since it has to support 12 input and 12 output terms, make the internal be something like a 9x9 grid of cells, maybe 3x27, or 18x18... something fairly small. Maybe support two-way pins... lol, quadstate output (-1, 0, 1, Z).

Anyway the goal is not a general purpose trinary FPGA, but a chip that can be programmed to be any reasonable 16 pin dip ssi type chip. (Oh, and these days the way economics of things are going, maybe actually do it all SOIC... dunno... DIPs are still more friendly to experimenters.)

And naturally, if I did it, it would be fully open source with gerbers for the chip available.

Jay


13 Dec 2010 23:55
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Shaos wrote:

I just a few weeks ago thought about that. My idea was to involve ternary multiplexers for LUTs and for interconnections plus ternary version of SPI might be used for programming and debugging.


Actually for the beginning I thought about ternary chip without flash or fuses inside, which is programmed "on boot" by memory chip connected through SPI (regular binary one). So it will be like ternary FPGA ;)


14 Dec 2010 23:45
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Because it uses fewer pins, and because I know there are EEPROMs that support it, I think I'd choose I2C over SPI. Though 1 wire is also attractive, I don't think there are memory chips that talk 1-wire commonly available.

In any case, how is this for a size/scale constraint: The chip will be big enough for a rom (mask programmed rom? EEPROM? flash? What's easy to do in mosis??) that implements an (open source) I2C (or other) 'boot loader'. So the right size chip is just barely big enough to implement it's own boot loader. Power on, it loads from or runs from rom implementing the boot loader. When it finishes loading it switches to the loaded image. So maybe we need to dedicate 3 pins: Reset (force a boot-load cycle), and the 2 I2C lines. This brings the overhead to 6 pins (3 power, 3 programing), so a 16 pin chip is getting a little small. Maybe go to 20 pin leaving 14 user defined pins. If you are clever, and depending on the design, the two pins for I2C might switch modes and take on some other function after rebooting...

Sounds like a fun chip to design. Wish I had the money to design and fab it... then I'd have to find a market for it... I suppose if it's done right you can make it work fine (with 3 voltage power) as a normal 2 voltage programmable binary chip. That would have a market. If there were a line of fully open source programmable chips, I think they would take over the lowend FPGA/PAL/GAL world.

I looked at open cores wondering how big a I2C protocol stack is and found:

http://opencores.org/project,i2c
Quote:
Synthesis results

Push-button synthesis results for various targets.

Actel:
- A54SX16ATQ100-std: 352Modules@58MHz

Altera:
- FLEX: EPF10K50ETC144-3: 294LCELLs@82MHz
- ACEX: EPF20K30ETC144-3: 257ATOMs@74MHz

Xilinx:
- Spartan-II: 2S15CS144-5: 229LUTs@82MHz
- Virtex-E: XCV50ECS144-8: 230LUTs@118MHz


If trinary really is more efficient maybe 27x9 (5 trit) = 243 programmable cells is enough. But 27x27 (6 trit) = 729 cells is the next logical cut off. I bet you could do a lot more than "typical SSI 74xx chips" using 729 trinary cells. Even if the cells didn't have memory elements, 729 cells is a lot of computing.

The ultimate in "dominate the world" compatible binary chip would actually signal the trinary values as 0, 2.5 and 5 V and have a single 5V (optional additional 2.5 V) supply. carefully tweaking the hardware could probably end up with a 5V ttl part seeing the 3 logic levels as 0, 1, 1. Internally the chip would be a 2.5 V CMOS design with -2.5, 0 and 2.5 "nominal" volts perhaps. Wow, do it right and you can have the chip talking 5V on some pins and 2.5V on others, you get a programmable glue chip that even does signaling domain translations for free.


15 Dec 2010 06:05
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SPI should be much much easier to implement in hardware (even from scratch). Also MOSIS offers packaging for 0.5 CMOS design in 2 options: DIP40 and DIP28, so I believe this chip must be DIP28. Also I thought to use RESET pin as programming pin:
+1 - RESET
0 - WORK
-1 - PROG


15 Dec 2010 08:55
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I checked open cores. The I2C implementation has the highest 'rating', the SPI implementation isn't as highly rated, and doesn't give figures for how big it is when implemented on FPGA's. But sure, I could live with SPI. 1 wire (adapted to trinary) still appeals to me on the pin count front. I like your 'muxing' of the reset/program/run pin. Maybe I'll 'design' the chip in logisim... There's really only an array of like 6 components: cells, wires, cross point switches, cell-to-wire connection, iocells/pads/pins, and (to me black magic) clock generation/distribution.


15 Dec 2010 18:52
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Yes, I forgot about clock... This chip will be SPI master, so it should send synchro out, but in order to do this, clock must be generated somewhere and probably outside of this chip. May be it has to be 2 separate clocks - one for programming and other for internal D-triggers for actual working...


16 Dec 2010 02:20
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Why would the clock have to be generated off chip? A clock generator is tiny compared to a FPGA/CPLD cell. The distribution tree is complicated, but your basic clock is not hard at all. And SPI is fairly relaxed about the clock, not like USB or anything. Probably a 555 equivalent would work fine.

But as I look at the original goals, then the souped up version that can implement I2C, SPI, 1 Wire... Maybe there is an easier way... Smaller cheaper chips... Not sure what it is, but most 74xx type glue logic chips don't need 700+ cells.

Maybe make the chips be serial-bus-slaves and be in-circuit programmable, and include flash or maybe just battery backed cmos ram. I don't know... Maybe keep is really really simple and when in program mode, all the storage in the chip is one giant shift register and you drive a clock and a data pin to shift the program in. But there's probably something really simple that would make sense for 9x9 sized chips. At 27x9 we can probably do fancy SPI/I2C etc. At 27x27 we def can.


16 Dec 2010 05:34
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Do you have a link for that estimate? And I'm guessing it would have to be purchased by some contracting/distribution company right?

I mean *through a contracting/distribution company. Like you have to do through cisco.


28 Oct 2011 14:05
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Jshep89 wrote:
Do you have a link for that estimate? And I'm guessing it would have to be purchased by some contracting/distribution company right?

I mean *through a contracting/distribution company. Like you have to do through cisco.



it was online quote service on their web-site - I entered my numbers and they e-mailed me their estimate for 1 run
P.S. if it will be serious intentions to create such chip I will register LLC for that purpose ;)
P.P.S. I just looked at their web-site again - actually mosis requires organization name in all forms, so probably yes - it has to be a company who does the purchase...


28 Oct 2011 14:31
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I know it might sound stupid, but I've done contracts where companies did payment plans for expensive equipment like networking equipment, blade servers, and etc. I wouldn't be surprised if it was possible to do something through MOSIS.


28 Oct 2011 15:30
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Jshep89 wrote:
I know it might sound stupid, but I've done contracts where companies did payment plans for expensive equipment like networking equipment, blade servers, and etc. I wouldn't be surprised if it was possible to do something through MOSIS.



Company is not a problem
I can create a company if I need too :)
Problem is to find investments ;)
P.S. At least we should have a prototype of some kind...


28 Oct 2011 15:35
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Even a prototype wouldn't be enough to obtain these kinds of investments. We'd need to do research on the practical applications for ternary computers/machines. As in what can they do that binary based machines cannot?


28 Oct 2011 21:14
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Some interesting info:

http://mightyohm.com/blog/2010/10/diy-i ... ith-mosis/


02 Nov 2011 00:32
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