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nedoPC.orgElectronics hobbyists community established in 2002 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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В 2002 году я на форуме opencores.org задал вопрос про открытую архитектуру FPGA и получил вот такой ответ:
| | | | Quote: As well as Marko and Damjan's Opencores one, there is Reinoud Lamberts' "open source design for an FPGA to be implemented on an FPGA". Reinoud calls it the MPGA. http://ce.et.tudelft.nl/~reinoud/mpga/README.shtmlThis has been tested in hardware, using a BurchED board. Hope that is of interest, Best regards Tony Burch http://www.BurchED.comFPGA boards, for System-On-Chip prototyping and education | | | | |
Битая ссылка на проект: ce.et.tudelft.nl/~reinoud/mpga/
Т.е. одно из решений добавления открытой структуры в закрытую архитектуру - это реализация на закрытой архитектуре программируемой открытой архитектуры, правда с избыточностью, т.к. прошивка для прошивки будет как бы эмулятором (с другой стороны FPGA уже является псевдо-хардверной эмуляцией через софтверное программирование микровычислителей - LUT-ов).
Last edited by Shaos on 24 Jan 2015 09:04, edited 4 times in total.
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05 Mar 2005 09:08 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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Проект не обновлялся с 2001 года и видимо уже закрыт
Что если нам самим сделать что-то подобное? Т.е. написать на VHDL описание некоего гипотетического FPGA (или свой проект решения проблемы перепрограммируемой логики), который было бы удобно программировать "вручную" - для начала можно прогонять эту прошивку на существующих FPGA или CPLD платах, а если у кого большие деньги появятся - можно и в реальном железе заказать промышленное производство
Last edited by Shaos on 03 Jan 2010 18:04, edited 1 time in total.
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05 Mar 2005 09:38 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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По аналогии с названием "Trinity" для гипотетического троичного компьютера, предлагаю самодельному компьютеру с перепрограммируемой архитектурой дать рабочее название "Morpheus" (игра слов всем понятна, надеюсь ; ).
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06 Mar 2005 00:22 |
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CHRV
God
Joined: 29 Dec 2003 01:00 Posts: 1101 Location: Москва
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Тут самые деньги собственно стоит софт для интерпретации VHDL или еще чегото на твои базовые ячейки. А БМК можно заказать и разработать, был бы хороший софт. Собственно сперва можно софт откатать например на стандартных FPGA а потом уже заниматься вложением денег, но вообще дело перспективное, но нужно какието интересные области занимать, типа скрещения аналоговых БМК и микроконтроллеров.
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09 Mar 2005 01:12 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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В том то и дело, что я не хочу иметь VHDL на мои базовые ячейки! Архив битовой прошивки будет открыт и докумнтирован - пусть люди сами пишут свои PALASM-ы и PLDASM-ы Со своей же стороны сделать например редактор функциональных блоков, который будет преобразовываться в битовый образ прошивки гипотетического девайса, а также VHDL описание читалки и интерпретилки такой прошивки для запуска на существующих FPGA или CPLD - так сказать для отладки.
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09 Mar 2005 07:08 |
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CHRV
God
Joined: 29 Dec 2003 01:00 Posts: 1101 Location: Москва
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"Люди" врядли такое осилят. Тут серьезная работа должна быть. А макороячейка должна быть с "изюминкой", только при этом можно кусок рынка откусить (ATMEL например взяла более низкой ценой).
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09 Mar 2005 07:21 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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Может такой "изюминкой" может стать троичность? Правда наверное VHDL не сможет такое описать...
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13 Apr 2005 08:27 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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| | | | Shaos wrote: В 2002 году я на форуме opencores.org задал вопрос про открытую архитектуру FPGA и получил вот такой ответ: | | | | Quote: As well as Marko and Damjan's Opencores one, there is Reinoud Lamberts' "open source design for an FPGA to be implemented on an FPGA". Reinoud calls it the MPGA. http://ce.et.tudelft.nl/~reinoud/mpga/README.shtmlThis has been tested in hardware, using a BurchED board. Hope that is of interest, Best regards Tony Burch http://www.BurchED.comFPGA boards, for System-On-Chip prototyping and education | | | | |
Работающая ссылка на проект - http://ce.et.tudelft.nl/~reinoud/mpga/Т.е. одно из решений добавления открытой структуры в закрытую архитектуру - это реализация на закрытой архитектуре программируемой открытой архитектуры, правда с избыточностью, т.к. прошивка для прошивки будет как бы эмулятором (с другой стороны FPGA уже является псевдо-хардверной эмуляцией через софтверное программирование микровычислителей - LUT-ов). | | | | |
некоторое время назад вышеозначенная страничка умерла - сегодня я покопался в вебархиве.org и вытащил наружу несколько текстов и даже пару архивов (похоже битые):
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03 Dec 2007 20:27 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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README: | | | | Quote: MPGA - Meta Programmable Gate Array Version 0 This is an open source design for an FPGA to be implemented on an FPGA; a 'meta-FPGA' (hence the name). If you wonder whether something like that makes any sense, then chances are that it won't be useful to you. However, this MPGA has a few nice properties that 'real' FPGAs lack. It has open programming specs, and a bitstream format that's amazingly easy to edit. This means that you aren't bound by limitations of vendor tools. (If you wonder what those limitations are, don't worry, be happy;). The open specs and design can also be especially attractive for open source tool development. Another notable feature is that you can (re)program an MPGA as fast as you like (and are willing to spend bandwidth on). This is rather nice for reconfigurable computing or evolutionary design experiments. The density of the current MPGA is actually fairly high: one MPGA CLB is implemented using one Virtex CLB. Of course, the MPGA CLB can't offer all the functionality of a Virtex CLB, but does offer FFs, LUTs, and (independent) global routing. Local routing is probably the weakest part of the current design, a fair percentage of CLBs will be needed for local routing through the cell. Also, I'm unsure how well automatic routers will be able to deal with the limited routing structure. And don't expect MPGA designs to achieve particularly high clock frequencies: there will be many levels of logic in most designs, because routing switches are implemented with LUTs. The user-visible CLB logic is shown in figure 1. The LUTs and selector are programmable; the FFs are simple positive edge triggered D flip-flops. The F output is used for local connections, the G output for global interconnect. CLB user logic Figure 1: CLB user logic. Note that the interconnect structure as described below actually depends on configuration parameters, and will probably change in the future. The A LUT inputs connect to the F CLB outputs of the local cluster (a cluster is a section of 2x2 CLBs). Three of the B LUT inputs connect to F outputs from adjacent clusters; one connects to the local G output. The C LUT connects to G outputs a distance of 6 CLBs away, in four directions. This way, the G network provides for independent global (long distance) routing. Local routing details are shown in figure 2. Each tile of the grid represents one CLB; cluster borders are emphasized. The B LUT connections for center cluster CLBs are indicated with symbols showing to which CLB in the center cluster they belong. B LUT local routing Figure 2: B LUT local routing. The ASCII bitstream format, see figure 3, shows the interconnect structure in full detail. LUTs are represented as Karnaugh maps, FFs as '[]'. The top left CLB of each cluster is marked with an MPGA logo. Two clusters are shown in the figure. ASCII bitstream format Figure 3: ASCII bitstream format. The MPGA project is currently in a larval stage. The code is a mess, and many important features are lacking (see TODO). Right now it is more a proof of concept than something fit for use. However, it works as far as tested, there's a parametrized MPGA core generator, there's support for simulation and downloading to hardware, there is even a tiny example design. At this point I would like to get some feedback, so please have a look. You're also welcome to improve things as you see fit (as long as you give changes back). You can mail me at reinoud@remove.et.tudelft.nl (no, don't remove the 'remove' in there;). Please be warned that YOU CAN BLOW UP YOUR EXPENSIVE HARDWARE if you aren't careful with the MPGA as it is now. It's all too easy to download a design with (unintended) combinatorial loops in it, there is no DRC, no warning. Worse, during the download process itself, there can be transient conditions with combinatorial feedback in an otherwise clean design. These 'transient' conditions may last longer than you'd like, with the current unfinished controller and download software (they were designed with safe operation in mind but not quite there yet). Resulting oscillations may cause widespread high frequency switching and this may draw more power than your hardware was designed to handle. So without proper precautions you might fry your expensive FPGAs, power supplies, or PCBs. It's probably best to use a power supply that limits current to safe levels, or to keep the MPGA core and connected logic small enough to be safe. The default core configuration in the source is quite small, you may want to keep it that way for now. Anyway, be careful. See HOWTO for details on how to configure, build and use the MPGA. Core generation, simulation, downloading and testing are done in a Linux environment, synthesis and P&R are done with Xilinx Foundation tools. The current MPGA is written in C and Verilog, targets Virtex and alikes, and is set up to use the BED-SPARTAN2+ board from BurchED (the nice new models may work too). This development is funded in part by STW / NWO and Delft University in the Netherlands, as part of the MOVE project. Although he is probably blissfully unaware of this little project, I would like to thank Stephen Williams for Icarus Verilog. Special thanks for interesting discussions and suggestions go to Graham Seaman of Open Collector fame. Thanks to Rogier Wolff for sharing his Linux expertise. And many thanks to Henk Corporaal for supporting this crazy little project. This work is dedicated to Jean Pierre Veen, our benevolent Program Officer at STW, who died shortly before the initial MPGA release. The MPGA is licensed under the Design Science License. The DSL is a generalised GPL, covering more than just software; see http://dsl.org/copyleft/ for more information. Copyright © 2001 Reinoud Lamberts This information may be copied, distributed and/or modified under certain conditions, but it comes WITHOUT ANY WARRANTY; see the Design Science License for more details. Any trademarks are the property of their respective owners. | | | | |
Last edited by Shaos on 03 Dec 2007 20:39, edited 1 time in total.
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03 Dec 2007 20:30 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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HOWTO:
| | | | Code: Conventions -----------
This text assumes you are in a Linux environment by default. Shell commands are represented in quotes, like this: "ls". The top level directory of the mpga distribution is represented as $MPGA.
Binary distro -------------
The binary distribution has everything pre-built, except for the simulation library files in $MPGA/sim/xil (which require files from the Foundation tools).
Requirements ------------
To build and test an MPGA as described below you need the following:
- A Linux system with ppdev/parport drivers, i.e. with kernel 2.4+ (or 2.2.17 with the ppdev patch). - Icarus Verilog (http://icarus.com/eda/verilog/). - Xilinx Foundation 3.x tools with synthesis (most likely running on windows). - A burched.com.au BED-SPARTAN2+ FPGA board. Newer versions of this board will probably also work, but I haven't verified this. - Preferrably two parallel ports, although it's possible to manage with just one. You'll also need an extra parallel port -> IDC26 cable or an extra download cable to use the 2 ports.
---------------------------------------------------------------------
Configuration -------------
The MPGA core configuration is specified in mpga_config.h. However, it's best to leave the configuration as it is; other parts of the current test design assume that the default config is used. Be careful when using large cores (see README).
Building cores --------------
Build the cores with "./b" in $MPGA (sorry, no makefiles yet). You can find the result in $MPGA/cout.
Preparing simulation --------------------
Make sure the filesystem with the Xilinx Foundation installation is mounted, and that $XILINX points to the Foundation installation directory. Go to $MPGA/sim, and run "./b" there to fetch and patch the necessary files for simulation with Icarus Verilog. You can find the results in $MPGA/sim/xil.
Go back to $MPGA and run "./v" there to build a simulation executable. This may take a while. Go to $MPGA/download and run "./b" there to build download and test executables.
Simulation ----------
Execute "./mpga_testbench" in $MPGA and keep it running (background, separate shell). Go to $MPGA/download and run "./lmpsim 8 6 ../pipes/ example.mbt". This downloads the design in example.mbt to the simulated 8x6 MPGA core, through named pipes. It may take a little while to do so.
In $MPGA/download, run "./stimsim ../pipes/ example.stm >vecs". This applies test stimuli in example.stm to the MPGA under test, and dumps the results in the vecs file. Compare them with the reference $MPGA/download/example.vecs; they should be the same.
Kill the mpga_testbench process when you're finished.
Implementation --------------
This section assumes that you know how to deal with the Xilinx Foundation tools. For implementation you'll need the following Verilog files:
$MPGA/mpga_bufs17.v $MPGA/mpga_clb_ASVT.v $MPGA/mpga_extop.v $MPGA/mpga_progctl.v $MPGA/cout/mpga_core_ASVT_CDPg6p4h8v6.v $MPGA/cout/mpga_progbuf_Sh8.v
To lock pins for the BurchED board and to get good CLB placement, merge and use the following UCF files:
$MPGA/mpga_extop.ucf $MPGA/cout/mpga_core_ASVT_CDPg6p4h8v6.ucf
Synthesize with the following settings:
toplevel = mpga_extop device = SPARTAN2, 2S200PQ208
You'll get lots of warnings about unconnected nets that will be tied to zero. That's okay (the experimental toplevel connects only a few inputs to the core).
Implement with the following:
Implementation Options: uncheck 'Use Timing Constraints During Place and Route'
Configuration Options: check 'Produce ASCII Configuration File'
You cannot use timing constraints because of the many false combinatorial feedback paths. Note that because of these paths static timing analysis produces bogus results.
Maybe it's a good idea to check if the pins have actually been locked correctly for the board before downloading.
Download and test -----------------
In this section the following assumptions are made:
- The .rbt bitstream file that has been produced before is in $MPGA/download and named mpga_2S200PQ208.rbt. - The download cable connects to the parallel port associated with /dev/parport1. - The test cable connects to the parallel port associated with /dev/parport0. - All commands are run in $MPGA/download.
In case you only have one parallel port, you will have to switch cables between downloading and testing. I don't recommend this, and haven't tried it myself. Be very careful that you maintain a common ground between the PC and FPGA board, so that you won't disturb or fry things during (un)plugging.
Use a Xilinx Parallel Cable III or compatible cable (the one supplied with the BurchED board will do) for downloading. Make sure that the bitstream file you will be downloading is for the right type of FPGA.
For testing, use a parallel port -> IDC26 cable like the one supplied as part of the BurchED download cable, and connect it to J5 on the BED-SPARTAN2+ board.
Run "./lxp mpga_2S200PQ208.rbt /dev/parport1" to download the MPGA to the FPGA over the programming cable. If everything goes well, there will be no warning messages from lxp, and the test led on the BurchED board will light up.
To download the design in example.mbt to the MPGA over the test cable, run "./lmp 8 6 /dev/parport0 example.mbt".
Next, run "./stim /dev/parport0 example.stm >vecs", to apply the test stimuli in example.stm to the MPGA over the test cable. Compare the results in vecs with the reference example.vecs. If they are the same, you have a working MPGA, congratulations!
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TODO:
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03 Dec 2007 20:38 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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В связи с этим хочется предложить на всеобщее обсуждение идею переконфигурируемого компьютера "Морфеус", который может быть перепрограммирован пользователем (причём с этого же самого компьютера) путём записи некоторых значений в ячейки распределённой памяти (есть в Spartan-3 от Xilinx) для перестраивания сети, содиняющей вместе логические и арифметические блоки, включая умножители 18x18 (есть несколько в Spartan-3 от Xilinx) - пользователю для этого не нужна среда разработки от Xilinx, как и знание VHDL - всё будет делаться "над" конкретной физической реализацией - поэтому с некоторой избыточностью, что можно в той или иной степени скрыть путём использования очень большой FPGA (например Spartan-3 с 200 тысячами гейтов или даже больше).
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04 Dec 2007 17:35 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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а вообще смотреть на эти максплюсы от альтеры или на вебпаки от зайлинкса без слёз невозможно - например за последние 10-15 лет разработка программ шагнула далеко вперёд (правда не так далеко как само железо), а вот эти среды разработки программируемой логики сидят где-то глубоко в прошлом веке - хотя кто знает, может есть и нормальные среды (за нормальные бабки)
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03 Jan 2010 17:44 |
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d_wanderer
Senior
Joined: 28 Feb 2006 21:34 Posts: 180
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Конечно есть. И совсем не плохие. НАпример качество оптимизации у одиозного Altium гораздо лучше чем у квартуса...
А есть ведь и сильно специализированные... Ну соответственно и стоимость....
Халявных продуктов такого класса просто не бывает...
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04 Jan 2010 05:48 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22587 Location: Silicon Valley
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Я не качество оптимизации имел ввиду, а способность упрощать жизнь разработчику - там визуальное представление, вменяемые и гибкие средства отладки, подсказки, анализаторы всякие и т.д.
P.S. Прочитал про Altium - по описанию интересно, но конкретного ничего не нашёл (чтобы с картинками о самом процессе разработки)
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04 Jan 2010 20:48 |
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d_wanderer
Senior
Joined: 28 Feb 2006 21:34 Posts: 180
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Странно, что фирма не рекламирует свои технологии... ))
На фирме мы как раз его используем для разработки. Достаточно удобно - нормально построенные библиотеки - неплохой отладчик симулято и куча всяких примочек....
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06 Jan 2010 08:32 |
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