nedoPC.org

/* xemul.h - Emulation of X output (03-DEC-2013) A.A.Shabarshin <ashabarshin@gmail.com> */

#ifndef __XEMUL_H
#define __XEMUL_H

#define _T_ (-1) /* TRUE */
#define _F_ (0) /* FALSE */
#define _R_EDGE (1) /* RISING EDGE */
#define _F_EDGE (-2) /* FALLING EDGE */

#define AND &&
#define OR ||
#define NOT ~

#define BIT(X) ((X)?1:0)
#define CHR(X) ((X>0)?'^':((!X)?'0':((X==_T_)?'1':((X==_F_EDGE)?'v':'?'))))

/*

FDCPE(Q,D,C,CLR,PRE,CE):

 CLR PRE CE D C  Q
 -----------------
  1   X   X X X  0
  0   1   X X X  1
  0   0   0 X X  stored
  0   0   1 D ^  D

*/

#define FDCPE(Q,D,C,R,S,E) ((R)?_F_:((S)?_T_:(((E)&&(C)>0)?((D)?_T_:_F_):((Q)?_T_:_F_))))

/*

FTCPE(Q,T,C,CLR,PRE,CE):

 CLR PRE CE T C  Q
 -----------------
  1   X   X X X  0
  0   1   X X X  1
  0   0   0 X X  stored
  0   0   1 0 X  stored
  0   0   1 1 ^  toggle

*/

#define FTCPE(Q,T,C,R,S,E) ((R)?_F_:((S)?_T_:(((E)&&(T)&&(C)>0)?((Q)?_F_:_T_):((Q)?_T_:_F_))))

/*

LDCP(Q,D,G,CLR,PRE):

 CLR PRE G D  Q
 --------------
  1   X  X X  0
  0   1  X X  1
  0   0  1 D  D
  0   0  0 X  stored

*/

#define LDCP(Q,D,G,R,S) ((R)?_F_:((S)?_T_:((G)?((D)?_T_:_F_):((Q)?_T_:_F_))))

#endif

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter2 is
    Port ( CLR : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           CEN : in  STD_LOGIC;
           OUTPUT : out  STD_LOGIC_VECTOR(9 downto 0));
end counter2;

architecture Behavioral of counter2 is
signal tmp : STD_LOGIC_VECTOR(9 downto 0);
begin

process (CLR,CLK,CEN) is
begin
if CLR='0' then -- Reset
   tmp <= "0000000000";
elsif CLK'event and CLK='0' and CEN='1' then
   tmp <= tmp + 1;
end if;
end process;

OUTPUT <= tmp;

end Behavioral;

#include <stdio.h>
#include "xemul.h"

int main(int argc, char **argv)
{
 int i,k = 100;

 int CLR = _T_;
 int CEN = _T_;
 int CLK = _F_;
 int _OUTPUT0,OUTPUT0 = 0;
 int _OUTPUT1,OUTPUT1 = 0;
 int _OUTPUT2,OUTPUT2 = 0;
 int _OUTPUT3,OUTPUT3 = 0;
 int _OUTPUT4,OUTPUT4 = 0;
 int _OUTPUT5,OUTPUT5 = 0;
 int _OUTPUT6,OUTPUT6 = 0;
 int _OUTPUT7,OUTPUT7 = 0;
 int _OUTPUT8,OUTPUT8 = 0;
 int _OUTPUT9,OUTPUT9 = 0;

 if(argc>1) k = atoi(argv[1]);

 for(i=0;i<k;i++)
 {

  switch(i%10)
  {
    case 0: CLK = _F_; break;
    case 1: CLK = _F_; break;
    case 2: CLK = _F_; break;
    case 3: CLK = _F_; break;
    case 4: CLK = _R_EDGE; break;
    case 5: CLK = _T_; break;
    case 6: CLK = _T_; break;
    case 7: CLK = _T_; break;
    case 8: CLK = _T_; break;
    case 9: CLK = _F_EDGE; break;
  }

  _OUTPUT0 = FTCPE(OUTPUT0,_T_,NOT CLK,NOT CLR,_F_,CEN);

  _OUTPUT1 = FTCPE(OUTPUT1,OUTPUT0,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T2 \
 (OUTPUT0 AND OUTPUT1)

  _OUTPUT2 = FTCPE(OUTPUT2,OUTPUT_T2,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T3 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2)

 _OUTPUT3 = FTCPE(OUTPUT3,OUTPUT_T3,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T4 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3)

 _OUTPUT4 = FTCPE(OUTPUT4,OUTPUT_T4,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T5 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \
  OUTPUT4)

 _OUTPUT5 = FTCPE(OUTPUT5,OUTPUT_T5,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T6 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \
  OUTPUT4 AND OUTPUT5)

 _OUTPUT6 = FTCPE(OUTPUT6,OUTPUT_T6,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T7 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \
  OUTPUT4 AND OUTPUT5 AND OUTPUT6)

 _OUTPUT7 = FTCPE(OUTPUT7,OUTPUT_T7,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T8 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \
  OUTPUT4 AND OUTPUT5 AND OUTPUT6 AND OUTPUT7)

 _OUTPUT8 = FTCPE(OUTPUT8,OUTPUT_T8,NOT CLK,NOT CLR,_F_,CEN);

#define OUTPUT_T9 \
 (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \
  OUTPUT4 AND OUTPUT5 AND OUTPUT6 AND OUTPUT7 AND OUTPUT8)

 _OUTPUT9 = FTCPE(OUTPUT9,OUTPUT_T9,NOT CLK,NOT CLR,_F_,CEN);

 OUTPUT0 = _OUTPUT0;
 OUTPUT1 = _OUTPUT1;
 OUTPUT2 = _OUTPUT2;
 OUTPUT3 = _OUTPUT3;
 OUTPUT4 = _OUTPUT4;
 OUTPUT5 = _OUTPUT5;
 OUTPUT6 = _OUTPUT6;
 OUTPUT7 = _OUTPUT7;
 OUTPUT8 = _OUTPUT8;
 OUTPUT9 = _OUTPUT9;

 printf("%i) %c %c %c (%c) -> %c %c %c %c %c %c %c %c %c %c\n", i,
        CHR(CLR),CHR(CEN),CHR(CLK),CHR(NOT CLK),
        CHR(OUTPUT0),CHR(OUTPUT1),CHR(OUTPUT2),CHR(OUTPUT3),CHR(OUTPUT4),
        CHR(OUTPUT5),CHR(OUTPUT6),CHR(OUTPUT7),CHR(OUTPUT8),CHR(OUTPUT9));

 }

 return 0;
}

0) 1 1 0 (1) -> 0 0 0 0 0 0 0 0 0 0
1) 1 1 0 (1) -> 0 0 0 0 0 0 0 0 0 0
2) 1 1 0 (1) -> 0 0 0 0 0 0 0 0 0 0
3) 1 1 0 (1) -> 0 0 0 0 0 0 0 0 0 0
4) 1 1 ^ (v) -> 0 0 0 0 0 0 0 0 0 0
5) 1 1 1 (0) -> 0 0 0 0 0 0 0 0 0 0
6) 1 1 1 (0) -> 0 0 0 0 0 0 0 0 0 0
7) 1 1 1 (0) -> 0 0 0 0 0 0 0 0 0 0
8) 1 1 1 (0) -> 0 0 0 0 0 0 0 0 0 0
9) 1 1 v (^) -> 1 0 0 0 0 0 0 0 0 0
10) 1 1 0 (1) -> 1 0 0 0 0 0 0 0 0 0
11) 1 1 0 (1) -> 1 0 0 0 0 0 0 0 0 0
12) 1 1 0 (1) -> 1 0 0 0 0 0 0 0 0 0
13) 1 1 0 (1) -> 1 0 0 0 0 0 0 0 0 0
14) 1 1 ^ (v) -> 1 0 0 0 0 0 0 0 0 0
15) 1 1 1 (0) -> 1 0 0 0 0 0 0 0 0 0
16) 1 1 1 (0) -> 1 0 0 0 0 0 0 0 0 0
17) 1 1 1 (0) -> 1 0 0 0 0 0 0 0 0 0
18) 1 1 1 (0) -> 1 0 0 0 0 0 0 0 0 0
19) 1 1 v (^) -> 0 1 0 0 0 0 0 0 0 0
20) 1 1 0 (1) -> 0 1 0 0 0 0 0 0 0 0
21) 1 1 0 (1) -> 0 1 0 0 0 0 0 0 0 0
22) 1 1 0 (1) -> 0 1 0 0 0 0 0 0 0 0
23) 1 1 0 (1) -> 0 1 0 0 0 0 0 0 0 0
24) 1 1 ^ (v) -> 0 1 0 0 0 0 0 0 0 0
25) 1 1 1 (0) -> 0 1 0 0 0 0 0 0 0 0
26) 1 1 1 (0) -> 0 1 0 0 0 0 0 0 0 0
27) 1 1 1 (0) -> 0 1 0 0 0 0 0 0 0 0
28) 1 1 1 (0) -> 0 1 0 0 0 0 0 0 0 0
29) 1 1 v (^) -> 1 1 0 0 0 0 0 0 0 0
30) 1 1 0 (1) -> 1 1 0 0 0 0 0 0 0 0
31) 1 1 0 (1) -> 1 1 0 0 0 0 0 0 0 0
32) 1 1 0 (1) -> 1 1 0 0 0 0 0 0 0 0
33) 1 1 0 (1) -> 1 1 0 0 0 0 0 0 0 0
34) 1 1 ^ (v) -> 1 1 0 0 0 0 0 0 0 0
35) 1 1 1 (0) -> 1 1 0 0 0 0 0 0 0 0
36) 1 1 1 (0) -> 1 1 0 0 0 0 0 0 0 0
37) 1 1 1 (0) -> 1 1 0 0 0 0 0 0 0 0
38) 1 1 1 (0) -> 1 1 0 0 0 0 0 0 0 0
39) 1 1 v (^) -> 0 0 1 0 0 0 0 0 0 0
40) 1 1 0 (1) -> 0 0 1 0 0 0 0 0 0 0
41) 1 1 0 (1) -> 0 0 1 0 0 0 0 0 0 0
42) 1 1 0 (1) -> 0 0 1 0 0 0 0 0 0 0
43) 1 1 0 (1) -> 0 0 1 0 0 0 0 0 0 0
44) 1 1 ^ (v) -> 0 0 1 0 0 0 0 0 0 0
45) 1 1 1 (0) -> 0 0 1 0 0 0 0 0 0 0
46) 1 1 1 (0) -> 0 0 1 0 0 0 0 0 0 0
47) 1 1 1 (0) -> 0 0 1 0 0 0 0 0 0 0
48) 1 1 1 (0) -> 0 0 1 0 0 0 0 0 0 0
49) 1 1 v (^) -> 1 0 1 0 0 0 0 0 0 0
50) 1 1 0 (1) -> 1 0 1 0 0 0 0 0 0 0
51) 1 1 0 (1) -> 1 0 1 0 0 0 0 0 0 0
52) 1 1 0 (1) -> 1 0 1 0 0 0 0 0 0 0
53) 1 1 0 (1) -> 1 0 1 0 0 0 0 0 0 0
54) 1 1 ^ (v) -> 1 0 1 0 0 0 0 0 0 0
55) 1 1 1 (0) -> 1 0 1 0 0 0 0 0 0 0
56) 1 1 1 (0) -> 1 0 1 0 0 0 0 0 0 0
57) 1 1 1 (0) -> 1 0 1 0 0 0 0 0 0 0
58) 1 1 1 (0) -> 1 0 1 0 0 0 0 0 0 0
59) 1 1 v (^) -> 0 1 1 0 0 0 0 0 0 0
60) 1 1 0 (1) -> 0 1 1 0 0 0 0 0 0 0
61) 1 1 0 (1) -> 0 1 1 0 0 0 0 0 0 0
62) 1 1 0 (1) -> 0 1 1 0 0 0 0 0 0 0
63) 1 1 0 (1) -> 0 1 1 0 0 0 0 0 0 0
64) 1 1 ^ (v) -> 0 1 1 0 0 0 0 0 0 0
65) 1 1 1 (0) -> 0 1 1 0 0 0 0 0 0 0
66) 1 1 1 (0) -> 0 1 1 0 0 0 0 0 0 0
67) 1 1 1 (0) -> 0 1 1 0 0 0 0 0 0 0
68) 1 1 1 (0) -> 0 1 1 0 0 0 0 0 0 0
69) 1 1 v (^) -> 1 1 1 0 0 0 0 0 0 0
70) 1 1 0 (1) -> 1 1 1 0 0 0 0 0 0 0
71) 1 1 0 (1) -> 1 1 1 0 0 0 0 0 0 0
72) 1 1 0 (1) -> 1 1 1 0 0 0 0 0 0 0
73) 1 1 0 (1) -> 1 1 1 0 0 0 0 0 0 0
74) 1 1 ^ (v) -> 1 1 1 0 0 0 0 0 0 0
75) 1 1 1 (0) -> 1 1 1 0 0 0 0 0 0 0
76) 1 1 1 (0) -> 1 1 1 0 0 0 0 0 0 0
77) 1 1 1 (0) -> 1 1 1 0 0 0 0 0 0 0
78) 1 1 1 (0) -> 1 1 1 0 0 0 0 0 0 0
79) 1 1 v (^) -> 0 0 0 1 0 0 0 0 0 0
80) 1 1 0 (1) -> 0 0 0 1 0 0 0 0 0 0
81) 1 1 0 (1) -> 0 0 0 1 0 0 0 0 0 0
82) 1 1 0 (1) -> 0 0 0 1 0 0 0 0 0 0
83) 1 1 0 (1) -> 0 0 0 1 0 0 0 0 0 0
84) 1 1 ^ (v) -> 0 0 0 1 0 0 0 0 0 0
85) 1 1 1 (0) -> 0 0 0 1 0 0 0 0 0 0
86) 1 1 1 (0) -> 0 0 0 1 0 0 0 0 0 0
87) 1 1 1 (0) -> 0 0 0 1 0 0 0 0 0 0
88) 1 1 1 (0) -> 0 0 0 1 0 0 0 0 0 0
89) 1 1 v (^) -> 1 0 0 1 0 0 0 0 0 0
90) 1 1 0 (1) -> 1 0 0 1 0 0 0 0 0 0
91) 1 1 0 (1) -> 1 0 0 1 0 0 0 0 0 0
92) 1 1 0 (1) -> 1 0 0 1 0 0 0 0 0 0
93) 1 1 0 (1) -> 1 0 0 1 0 0 0 0 0 0
94) 1 1 ^ (v) -> 1 0 0 1 0 0 0 0 0 0
95) 1 1 1 (0) -> 1 0 0 1 0 0 0 0 0 0
96) 1 1 1 (0) -> 1 0 0 1 0 0 0 0 0 0
97) 1 1 1 (0) -> 1 0 0 1 0 0 0 0 0 0
98) 1 1 1 (0) -> 1 0 0 1 0 0 0 0 0 0
99) 1 1 v (^) -> 0 1 0 1 0 0 0 0 0 0

entity main is
    Port ( CLR : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           H0  : out STD_LOGIC;
           H1  : out STD_LOGIC;
           H2  : out STD_LOGIC;
           H3  : out STD_LOGIC;
           H4  : out STD_LOGIC;
           H5  : out STD_LOGIC;
           H6  : out STD_LOGIC;
           H7  : out STD_LOGIC;
           H8  : out STD_LOGIC;
           H9  : out STD_LOGIC;       
           V0  : out STD_LOGIC;
           V1  : out STD_LOGIC;
           V2  : out STD_LOGIC;
           V3  : out STD_LOGIC;
           V4  : out STD_LOGIC;
           V5  : out STD_LOGIC;
           V6  : out STD_LOGIC;
           V7  : out STD_LOGIC;
           V8  : out STD_LOGIC;
           V9  : out STD_LOGIC;
           VID : out STD_LOGIC;
           SYNC : out STD_LOGIC);
end main;

architecture Behavioral of main is
signal HTMP : STD_LOGIC_VECTOR(9 downto 0);
signal VTMP : STD_LOGIC_VECTOR(9 downto 0);
begin

process (CLR,CLK) is
begin
if CLR='0' then
   HTMP <= "0000000000";
   VTMP <= "0000000000";
   SYNC <= '1';
   VID <= '1';
elsif CLK'event and CLK='0' then
--   if HTMP<384 and VTMP<256 then
--      VID <= '1';
--   else
--      VID <= '0';
--   end if;
   HTMP <= HTMP + "0000000001";
   if HTMP="1010000001"   then -- 641
      VTMP <= VTMP + "0000000001";      
      HTMP <= "0000000000";
   end if;
   if VTMP="0100111000" then -- 321
      VTMP <= "0000000000";
   end if;
end if;
end process;

H0 <= HTMP(0);
H1 <= HTMP(1);
H2 <= HTMP(2);
H3 <= HTMP(3);
H4 <= HTMP(4);
H5 <= HTMP(5);
H6 <= HTMP(6);
H7 <= HTMP(7);
H8 <= HTMP(8);
H9 <= HTMP(9);

V0 <= VTMP(0);
V1 <= VTMP(1);
V2 <= VTMP(2);
V3 <= VTMP(3);
V4 <= VTMP(4);
V5 <= VTMP(5);
V6 <= VTMP(6);
V7 <= VTMP(7);
V8 <= VTMP(8);
V9 <= VTMP(9);

end Behavioral;

FTCPE_H0: FTCPE port map (H0,'1',NOT CLK,NOT CLR,'0');

FTCPE_H1: FTCPE port map (H1,H1_T,NOT CLK,NOT CLR,'0');
H1_T <= ((NOT H0)
   OR (NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));

FTCPE_H2: FTCPE port map (H2,H2_T,NOT CLK,NOT CLR,'0');
H2_T <= (H0 AND H1);

FTCPE_H3: FTCPE port map (H3,H3_T,NOT CLK,NOT CLR,'0');
H3_T <= (H0 AND H1 AND H2);

FTCPE_H4: FTCPE port map (H4,H4_T,NOT CLK,NOT CLR,'0');
H4_T <= (H0 AND H1 AND H2 AND H3);

FTCPE_H5: FTCPE port map (H5,H5_T,NOT CLK,NOT CLR,'0');
H5_T <= (H0 AND H1 AND H2 AND H3 AND H4);

FTCPE_H6: FTCPE port map (H6,H6_T,NOT CLK,NOT CLR,'0');
H6_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5);

FTCPE_H7: FTCPE port map (H7,H7_T,NOT CLK,NOT CLR,'0');
H7_T <= ((H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6)
   OR (H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND
   H9));

FTCPE_H8: FTCPE port map (H8,H8_T,NOT CLK,NOT CLR,'0');
H8_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6 AND H7);

FTCPE_H9: FTCPE port map (H9,H9_T,NOT CLK,NOT CLR,'0');
H9_T <= ((H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6 AND H7 AND H8)
   OR (H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND
   H9));


SYNC <= '1';

FTCPE_V0: FTCPE port map (V0,V0_T,NOT CLK,NOT CLR,'0');
V0_T <= ((NOT V4 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (NOT V5 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (NOT V8 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V7 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V9 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V0 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V1 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V2 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (NOT V3 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9)
   OR (V6 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9));

FTCPE_V1: FTCPE port map (V1,V1_T,NOT CLK,NOT CLR,'0');
V1_T <= (V0 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND
   NOT H8 AND H9);

FTCPE_V2: FTCPE port map (V2,V2_T,NOT CLK,NOT CLR,'0');
V2_T <= (V0 AND V1 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H7 AND NOT H8 AND H9);

FTCPE_V3: FTCPE port map (V3,V3_T,NOT CLK,NOT CLR,'0');
V3_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND
   NOT V9)
   OR (V0 AND V1 AND V2 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND
   NOT H6 AND H7 AND NOT H8 AND H9));

FTCPE_V4: FTCPE port map (V4,V4_T,NOT CLK,NOT CLR,'0');
V4_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND
   NOT V9)
   OR (V0 AND V1 AND V2 AND V3 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND
   NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));

FTCPE_V5: FTCPE port map (V5,V5_T,NOT CLK,NOT CLR,'0');
V5_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND
   NOT V9)
   OR (V0 AND V1 AND V2 AND V3 AND V4 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND
   NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));

FTCPE_V6: FTCPE port map (V6,V6_T,NOT CLK,NOT CLR,'0');
V6_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND H0 AND NOT H1 AND NOT H2 AND
   NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);

FTCPE_V7: FTCPE port map (V7,V7_T,NOT CLK,NOT CLR,'0');
V7_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND H0 AND NOT H1 AND
   NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);

FTCPE_V8: FTCPE port map (V8,V8_T,NOT CLK,NOT CLR,'0');
V8_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND
   NOT V9)
   OR (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7 AND H0 AND
   NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));

FTCPE_V9: FTCPE port map (V9,V9_T,NOT CLK,NOT CLR,'0');
V9_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7 AND V8 AND
   H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);


VID <= '1';

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE);
 FTCPE (Q,D,C,CLR,PRE,CE);
 LDCP  (Q,D,G,CLR,PRE);

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port ( CLR : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           H0  : out STD_LOGIC;
           H1  : out STD_LOGIC;
           H2  : out STD_LOGIC;
           H3  : out STD_LOGIC;
           H4  : out STD_LOGIC;
           H5  : out STD_LOGIC;
           H6  : out STD_LOGIC;
           H7  : out STD_LOGIC;
           H8  : out STD_LOGIC;
           H9  : out STD_LOGIC;       
           V0  : out STD_LOGIC;
           V1  : out STD_LOGIC;
           V2  : out STD_LOGIC;
           V3  : out STD_LOGIC;
           V4  : out STD_LOGIC;
           V5  : out STD_LOGIC;
           V6  : out STD_LOGIC;
           V7  : out STD_LOGIC;
           V8  : out STD_LOGIC;
           V9  : out STD_LOGIC;
           VID : out STD_LOGIC;
           SYNC : out STD_LOGIC);
end main;

architecture Behavioral of main is
signal HTMP : STD_LOGIC_VECTOR(9 downto 0);
signal VTMP : STD_LOGIC_VECTOR(9 downto 0);
signal HCLR : STD_LOGIC;
signal VCLR : STD_LOGIC;
begin

process (CLR,VCLR,HCLR,CLK) is
begin
if CLR='0' then
   HTMP <= "0000000000";
   VTMP <= "0000000000";
   HCLR <= '1';
   VCLR <= '1';
   SYNC <= '1';
   VID <= '1';
elsif HCLR='0' then
   HTMP <= "0000000000";
   HCLR <= '1';
   SYNC <= '1';
   VID <= '1';
elsif VCLR='0' then
   VTMP <= "0000000000";
   VCLR <= '1';
   SYNC <= '1';
   VID <= '1';
elsif CLK'event and CLK='0' then
   if HTMP<384 and VTMP<256 then
      VID <= '1';
   else
      VID <= '0';
   end if;
   if (VTMP>278 and VTMP<282) or
      (HTMP>464 and HTMP<512) then
      SYNC <= '0';
   else
      SYNC <= '1';
   end if;
   if HTMP=640   then
      HCLR <= '0';
      VTMP <= VTMP + 1;
   end if;
   if VTMP=311 then
      VCLR <= '0';
   end if;
   HTMP <= HTMP + 1;
end if;
end process;

H0 <= HTMP(0);
H1 <= HTMP(1);
H2 <= HTMP(2);
H3 <= HTMP(3);
H4 <= HTMP(4);
H5 <= HTMP(5);
H6 <= HTMP(6);
H7 <= HTMP(7);
H8 <= HTMP(8);
H9 <= HTMP(9);

V0 <= VTMP(0);
V1 <= VTMP(1);
V2 <= VTMP(2);
V3 <= VTMP(3);
V4 <= VTMP(4);
V5 <= VTMP(5);
V6 <= VTMP(6);
V7 <= VTMP(7);
V8 <= VTMP(8);
V9 <= VTMP(9);

end Behavioral;

********** Mapped Logic **********

FTCPE_H0: FTCPE port map (H0,'1',NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);

FTCPE_H1: FTCPE port map (H1,H0,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);

FTCPE_H2: FTCPE port map (H2,H2_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H2_T <= (H0 AND H1);

FTCPE_H3: FTCPE port map (H3,H3_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H3_T <= (H0 AND H1 AND H2);

FTCPE_H4: FTCPE port map (H4,H4_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H4_T <= (H0 AND H1 AND H2 AND H3);

FTCPE_H5: FTCPE port map (H5,H5_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H5_T <= (H0 AND H1 AND H2 AND H3 AND H4);

FTCPE_H6: FTCPE port map (H6,H6_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H6_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5);

FTCPE_H7: FTCPE port map (H7,H7_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H7_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);

FTCPE_H8: FTCPE port map (H8,H8_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H8_T <= (H0 AND H7 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);

FTCPE_H9: FTCPE port map (H9,H9_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
H9_T <= (H0 AND H7 AND H8 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);

FDCPE_HCLR: FDCPE port map (HCLR,'0',NOT CLK,'0',NOT HTMP(9)/HTMP(9)_RSTF__$INT,HCLR_CE);
HCLR_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND VCLR);


HTMP(9)/HTMP(9)_RSTF__$INT <= (HCLR AND CLR);

FDCPE_SYNC: FDCPE port map (SYNC,SYNC_D,NOT CLK,'0',NOT SYNC_OBUF/SYNC_OBUF_SETF__$INT);
SYNC_D <= ((H7 AND H8 AND H3 AND H4 AND H6 AND NOT H9)
   OR (NOT V1 AND NOT V2 AND V3 AND V8 AND V4 AND NOT V5 AND NOT V6 AND NOT V7 AND NOT V9)
   OR (V0 AND V1 AND V2 AND NOT V3 AND V8 AND V4 AND NOT V5 AND NOT V6 AND NOT V7 AND
   NOT V9)
   OR (H7 AND H8 AND H5 AND H6 AND NOT H9)
   OR (H0 AND H7 AND H8 AND H4 AND H6 AND NOT H9)
   OR (H7 AND H8 AND H1 AND H4 AND H6 AND NOT H9)
   OR (H7 AND H8 AND H2 AND H4 AND H6 AND NOT H9));


SYNC_OBUF/SYNC_OBUF_SETF__$INT <= (VCLR AND HCLR AND CLR);

FTCPE_V0: FTCPE port map (V0,'1',NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V0_CE);
V0_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V1: FTCPE port map (V1,V0,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V1_CE);
V1_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V2: FTCPE port map (V2,V2_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V2_CE);
V2_T <= (V0 AND V1);
V2_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V3: FTCPE port map (V3,V3_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V3_CE);
V3_T <= (V0 AND V1 AND V2);
V3_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V4: FTCPE port map (V4,V4_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V4_CE);
V4_T <= (V0 AND V1 AND V2 AND V3);
V4_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V5: FTCPE port map (V5,V5_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V5_CE);
V5_T <= (V0 AND V1 AND V2 AND V3 AND V4);
V5_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V6: FTCPE port map (V6,V6_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V6_CE);
V6_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5);
V6_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V7: FTCPE port map (V7,V7_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V7_CE);
V7_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6);
V7_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V8: FTCPE port map (V8,V8_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V8_CE);
V8_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7);
V8_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FTCPE_V9: FTCPE port map (V9,V9_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V9_CE);
V9_T <= (V0 AND V1 AND V2 AND V3 AND V8 AND V4 AND V5 AND V6 AND V7);
V9_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND
   H9 AND HCLR);

FDCPE_VCLR: FDCPE port map (VCLR,'0',NOT CLK,'0',NOT VTMP(9)/VTMP(9)_RSTF__$INT,VCLR_CE);
VCLR_CE <= (V0 AND V1 AND V2 AND NOT V3 AND V8 AND V4 AND V5 AND NOT V6 AND NOT V7 AND
   NOT V9 AND HCLR);

FDCPE_VID: FDCPE port map (VID,VID_D,NOT CLK,'0',NOT VID_OBUF/VID_OBUF_SETF__$INT);
VID_D <= ((NOT H7 AND NOT H9 AND NOT V8 AND NOT V9)
   OR (NOT H8 AND NOT H9 AND NOT V8 AND NOT V9));


VID_OBUF/VID_OBUF_SETF__$INT <= (VCLR AND HCLR AND CLR);


VTMP(9)/VTMP(9)_RSTF__$INT <= (VCLR AND CLR);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE);
 FTCPE (Q,D,C,CLR,PRE,CE);
 LDCP  (Q,D,G,CLR,PRE);

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    Port ( CLR : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           H0  : out STD_LOGIC;
           H1  : out STD_LOGIC;
           H2  : out STD_LOGIC;
           H3  : out STD_LOGIC;
           H4  : out STD_LOGIC;
           H5  : out STD_LOGIC;
           H6  : out STD_LOGIC;
           H7  : out STD_LOGIC;
           H8  : out STD_LOGIC;
           H9  : out STD_LOGIC;       
           V0  : out STD_LOGIC;
           V1  : out STD_LOGIC;
           V2  : out STD_LOGIC;
           V3  : out STD_LOGIC;
           V4  : out STD_LOGIC;
           V5  : out STD_LOGIC;
           V6  : out STD_LOGIC;
           V7  : out STD_LOGIC;
           V8  : out STD_LOGIC;
           V9  : out STD_LOGIC;
           VID : out STD_LOGIC;
           SYNC : out STD_LOGIC);
end main;

architecture Behavioral of main is
signal HTMP : STD_LOGIC_VECTOR(9 downto 0);
signal VTMP : STD_LOGIC_VECTOR(9 downto 0);
signal HCLR : STD_LOGIC;
signal VCLR : STD_LOGIC;
signal HSYNC : STD_LOGIC;
signal VSYNC : STD_LOGIC;
begin

process (VSYNC,HSYNC) is
begin
if VSYNC='1' or HSYNC='1' then
   SYNC <= '0';
else
   SYNC <= '1';
end if;
end process;

process (CLK,CLR,VCLR,HCLR) is
begin
if CLR='0' then
   HTMP <= "0000000000";
   VTMP <= "0000000000";
   HCLR <= '1';
   VCLR <= '1';
   VID <= '1';
elsif HCLR='0' then
   HTMP <= "0000000000";
   HCLR <= '1';
   VID <= '1';
elsif VCLR='0' then
   VTMP <= "0000000000";
   VCLR <= '1';
   VID <= '1';
elsif CLK'event and CLK='0' then
   if HTMP<384 and VTMP<256 then
      VID <= '1';
   else
      VID <= '0';
   end if;
   if VTMP>278 and VTMP<282 then
      VSYNC <= '1';
   else
      VSYNC <= '0';
   end if;
   if HTMP>464 and HTMP<512 then
      HSYNC <= '1';
   else
      HSYNC <= '0';
   end if;
   if HTMP=640   then
      HCLR <= '0';
      VTMP <= VTMP + 1;
   end if;
   if VTMP=311 then
      VCLR <= '0';
   end if;
   HTMP <= HTMP + 1;
end if;
end process;

H0 <= HTMP(0);
H1 <= HTMP(1);
H2 <= HTMP(2);
H3 <= HTMP(3);
H4 <= HTMP(4);
H5 <= HTMP(5);
H6 <= HTMP(6);
H7 <= HTMP(7);
H8 <= HTMP(8);
H9 <= HTMP(9);

V0 <= VTMP(0);
V1 <= VTMP(1);
V2 <= VTMP(2);
V3 <= VTMP(3);
V4 <= VTMP(4);
V5 <= VTMP(5);
V6 <= VTMP(6);
V7 <= VTMP(7);
V8 <= VTMP(8);
V9 <= VTMP(9);

end Behavioral;

>diff main.report0 main.report1
4c4
< Design Name: main                                Date: 12- 5-2013,  7:40AM
---
> Design Name: main                                Date: 12- 5-2013,  6:20AM
404,405c404,405
< VID_D <= ((NOT H7 AND NOT V8 AND NOT H9 AND NOT V9)
<    OR (NOT H8 AND NOT V8 AND NOT H9 AND NOT V9));
---
> VID_D <= ((NOT H7 AND NOT H9 AND NOT V8 AND NOT V9)
>    OR (NOT H8 AND NOT H9 AND NOT V8 AND NOT V9));

>diff main.jed0 main.jed1
2c2
< Date Extracted: Thu Dec  5 07:41:07 2013
---
> Date Extracted: Thu Dec  5 07:46:08 2013
384c384
< L0009760 00000000 00000000 00000001 00000000*
---
> L0009760 00000000 00000000 00000000 00000000*
1666,1667c1666,1667
< CF151*
< C6E5
---
> CF0D1*
> C6F2

< main.mfd:   !VSYNC.D = !V1 & !V2 & V3 & V8 & V4 & !V5 & !V6 & !V7 & !V9
---
> main.mfd:   VSYNC.D = !V1 & !V2 & V3 & V8 & V4 & !V5 & !V6 & !V7 & !V9