Текст VHDL получается абсолютно нечитаемый т.к. по сути это нетлист:
Code: Select all
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clk1: Ternary_Clock port map( B_C => tmp_clk, T_C => ss );
-- BLN
pclk(0) <= ss(0);
pclk(1) <= '0';
-- BLP
nclk(0) <= '0';
nclk(1) <= ss(1);
mux1: ternary_mux port map( T_S => clr, T_N => N, T_O => pclk, T_P => pclk, T_C => pclk1 );
-- BLN2
pclk0(0) <= pclk1(0);
pclk0(1) <= '0';
mux2: ternary_mux port map( T_S => clr, T_N => P, T_O => nclk, T_P => nclk, T_C => nclk1 );
mem1: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss0, T_Q => m1 );
ha1: Half_Adder port map( a => P, b => m1, s => h1, c => g1 );
mem2: ternary_mem port map( T_S => nclk1, T_N => h1, T_P => O, T_Q => ss0 );
mem3: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss1, T_Q => m2 );
ha2: Half_Adder port map( a => g1, b => m2, s => h2, c => g2 );
mem4: ternary_mem port map( T_S => nclk1, T_N => h2, T_P => O, T_Q => ss1 );
mem5: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss2, T_Q => m3 );
ha3: Half_Adder port map( a => g2, b => m3, s => h3, c => g3 );
mem6: ternary_mem port map( T_S => nclk1, T_N => h3, T_P => O, T_Q => ss2 );
mem7: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss3, T_Q => m4 );
ha4: Half_Adder port map( a => g3, b => m4, s => h4, c => g4 );
mem8: ternary_mem port map( T_S => nclk1, T_N => h4, T_P => O, T_Q => ss3 );
mem9: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss4, T_Q => m5 );
ha5: Half_Adder port map( a => g4, b => m5, s => h5, c => g5 );
mem10: ternary_mem port map( T_S => nclk1, T_N => h5, T_P => O, T_Q => ss4 );
mem11: ternary_mem port map( T_S => pclk1, T_N => O, T_P => ss5, T_Q => m6 );
ha6: Half_Adder port map( a => g5, b => m6, s => h6, c => g6 );
mem12: ternary_mem port map( T_S => nclk1, T_N => h6, T_P => O, T_Q => ss5 );
dmux1: ternary_dmux port map( T_S => com4, T_C => pclk0, T_N => dm1, T_O => dm2, T_P => dm3 );
dmux2: ternary_dmux port map( T_S => com3, T_C => dm1, T_N => dNN, T_O => dNO, T_P => dNP );
dmux3: ternary_dmux port map( T_S => com3, T_C => dm2, T_N => dON, T_O => dOO, T_P => dOP );
dmux4: ternary_dmux port map( T_S => com3, T_C => dm3, T_N => dPN, T_O => dPO, T_P => dPP );
mux3: ternary_mux port map( T_S => asign, T_N => dOO, T_O => O, T_P => O, T_C => mu3 );
dmux5: ternary_dmux port map( T_S => ic2, T_C => mu3, T_O => dm0, T_P => dm00 );
dmux6: ternary_dmux port map( T_S => ic1, T_C => dm0, T_O => dm4, T_P => dm5 );
dmux7: ternary_dmux port map( T_S => ic1, T_C => dm00, T_N => dm6, T_O => dm7, T_P => dm8 );
dmux8: ternary_dmux port map( T_S => ic0, T_C => dm4, T_P => wr1 );
dmux9: ternary_dmux port map( T_S => ic0, T_C => dm5, T_N => wr2, T_O => wr3, T_P => wr4 );
dmux10: ternary_dmux port map( T_S => ic0, T_C => dm6, T_N => wr5, T_O => wr6, T_P => wr7 );
dmux11: ternary_dmux port map( T_S => ic0, T_C => dm7, T_N => wr8, T_O => wr9, T_P => wr10 );
dmux12: ternary_dmux port map( T_S => ic0, T_C => dm8, T_N => wr11, T_O => wr12, T_P => wr13 );
mux4: ternary_mux port map( T_S => com1, T_N => N, T_O => com0, T_P => P, T_C => mu4 );
mux5: ternary_mux port map( T_S => com2, T_N => N, T_O => mu4, T_P => P, T_C => asign );
mux7: ternary_mux port map( T_S => com2, T_N => O, T_O => asign, T_P => O, T_C => mu7 );
mux8: ternary_mux port map( T_S => com1, T_N => O, T_O => mu7, T_P => O, T_C => mu8 );
mux9: ternary_mux port map( T_S => asign, T_N => mu8, T_O => asign, T_P => asign, T_C => mu9 );
inv2: ternary_mux port map( T_S => com0, T_N => P, T_O => O, T_P => N, T_C => ic0 );
inv3: ternary_mux port map( T_S => com1, T_N => P, T_O => O, T_P => N, T_C => ic1 );
inv4: ternary_mux port map( T_S => com2, T_N => P, T_O => O, T_P => N, T_C => ic2 );
mux17: ternary_mux port map( T_S => com4, T_N => N, T_O => com3, T_P => P, T_C => osign );
min1: ternary_min port map( T_A => dOO, T_B => mu9, T_C => mi1 );
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Видимо надо какой-то редактор схемного ввода городить, который позволял бы быстро переходить из графического представления в текстовое и обратно, а то дополнять такую "схему" в будущем будет нереально, а тем более исправлять в ней ошибки...
