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Single-wire Balanced Ternary Circuits with Opamps 
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Junior

Joined: 20 Nov 2018 04:58
Posts: 2
Location: Saint-Petersburg, Russia
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Hello All !

After about a decade of watching this forum and on-and-off thinking about ternary electronics, I have decided to tinker with actual ternary hardware (and software) myself.

Since we all live in a binary-dominated world, it would be too much to try to design and build everything from scratch (especially memory), but at the same time it feels "unfair" to use Binary Coded Ternary exclusively.

I have an ongoing project to design and manufacture a small PCB-based ternary CPU with a reasonable external I/O (by reasonable I mean something which can be connected to a usual PC for printing something and reading machine code sent over a USB). Since on this forum there are already a Triador project, Lavr's 4-trit CPU and the original TriMux, I have shifted my efforts towards Binary-to-Ternary interfacing and simple-as-possible logic gates using diode-resistor logic backed up by conventional operational amplifiers.

The current state of affairs is available on YouTube in a form of a playlist:

https://www.youtube.com/watch?v=EVDI0rgQXcQ&list=PLwgb0qEIYnq-t7R9lRGmh-Czmdxo74yCD

There are both Ternary-To-Binary and Binary-To-Ternary hardware converters (3Trits to 5Bits, 5Trits to 8Bits), some basic gates (Min/Max, aka AND/OR, Sum,Any,Consensus - all that is necessary for building an ALU) and an alternative opamp-only design for the multiplexer. The general idea is to use binary SRAM/EEPROM chips as much as possible, while converting their inputs and outputs to ternary. There is also a Ternary-to-Binary-to-Ternary bidirectional transceiver circuit to allow 74244-like functionality for a bus-based CPU/SoC design.

Since I am a self-taught electronics enthusiast (Math/SoftwareEngineering by trade), I suspect the designs are far from being complete. Some of the circuits I present I have built and tested on the breadboards, but I also realize the obvious problems: opamp zero-drift, slew rate edge rise times etc. I hope these can be addressed later, when the alpha-version of the CPU (for which there are pretty much all the necessary circuits) is available.

As the project progresses, I will make more information available.


08 Nov 2021 12:18
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