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research at IEEE and Shanghai university 
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Novelist

Joined: 11 Apr 2014 16:57
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It seems like quite a few people are turning to ternary logic for quantum and optical computers. Do you guys think their research will grow legs?


16 Apr 2014 02:26
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I moved topic to English section

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16 Apr 2014 07:16
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Off-topic removed ;)

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16 Apr 2014 13:41
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Novelist

Joined: 11 Apr 2014 16:57
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http://iopscience.iop.org/1402-4896/2005/T118/025/pdf/physscr5_T118_025.pdf

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5954236&queryText%3Dternary

http://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=true&queryText=ternary+quantum


Just a few links last one is just a basic search of IEEE

So what I was trying to ask is does anyone think this research will go anywhere?


16 Apr 2014 15:14
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Junior
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But, does he know how to switch plugins? He seems to be someone who thinks as most people do that it is what it is, and no changing it.

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11 Oct 2015 14:02
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GeorgeMen wrote:
But, does he know how to switch plugins? He seems to be someone who thinks as most people do that it is what it is, and no changing it.


what? are you bot?...

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11 Oct 2015 19:11
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Doomed
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Hybrid Signed–Digit Number Systems:

A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains
Dhananjay S. Phatak Electrical Engr. Dept., State University of New York Binghamton, NY 1302–6000
phatak@ee.binghamton.edu Israel Koren, Fellow, IEEE Department of Electrical and Computer Engineering
University of Massachusetts, Amherst, MA 01003 (IEEE Transactions on Computers, vol. 43, No. 8, August 1994
pp 880-891)

ABSTRACT

A novel hybrid number representation is proposed in this paper. It includes the two’s complement
representation and the signed-digit representation as special cases. The hybrid number representations
proposed are capable of bounding the maximum length of carry propagation chains during addition to
any desired value between 1 and the entire word length. The framework reveals a continuum of number
representations between the two extremes of two’s complement and signed-digit number systems and
allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers
and alike.

We present several static CMOS implementations of a two–operand adder which employ the pro-
posed representations. We then derive quantitative estimates of area (in terms of the required number
of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illus-
trates the tradeoffs between area and execution time associated with each of the possible representations.
We also discuss adder trees for parallel multipliers and show that the proposed representations lead to
compact adder trees with fast execution times.

In practice, the area available to a designer is often limited. In such cases, the designer can select the
particular hybrid representation that yields the most suitable implementation (fastest, lowest power con-
sumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined,
the designer can select a hybrid representation that minimizes area or power under the delay constraint.

Index terms : Bounded Carry Propagation, Carry–free addition, Hybrid Signed–Digit Number
System, Redundant Number Representation, Signed–Digit Numbers, Static CMOS implementation.

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06 Jun 2022 23:17
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