In February 2006 I designed ternary ADC module (discussed at that time in russian topic of our forum as conversion of some binary ADC principles to ternary ADC scheme) that takes analog signal and produces 1 trit and analog error that can be connected to next ADC module to produce next 1 trit and next analog error - precision of this solution and number of possible tritness are unknown:
You can see 2 op-amp, 2 comparators and 2 diodes per 1 produced trit. Scheme was tested in MULTISIM and it looks working, but in real life I think we need to add one more op-amp before ternary output to buffer it from next scheme (or simple ternary buffer with 2 bipolar transistors - PNP and NPN).
You can see source of analog signal at the left bottom corner of scheme. Signal connected to operational amplifier in inverter mode with gain 1. Then it comes to ternary inverter that consists of 2 comparators and 2 diodes (left upper side) with thresholds -U/3 and +U/3. Output of ternary inverter is connected to operational amplifier in inverter mode that are summing signals by this expression:
Uout = -3*(-Uin) - 2*Uinv3 = 3*Uin - 2*Uinv3
where -Uin - inverted input signal, Uinv3 - output of ternary inverter (that ternary inverts inverted input signal).
Output of ternary inverter (point between 2 diodes from which you can see connection to virtual voltmeter) is actual 1 trit output of ADC module.
Output of summing amplifier Uout may be used as error that is normalized to power range -U...+U and that can be used to get next 1 trit using similar ADC module along with next normalized error that can be used farther.
