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5500FP Ternary CPU board. 
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Joined: 04 Jan 2016 10:15
Posts: 278
Location: Russia, S.- Peterburg
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To overcome Moore's law, it is necessary to use innovative technologies.
We are addressing the problem by increasing the density of information. For this reason, we used the ternary system (instead of the binary).
We have achieved amazing results, the capacity of our prototype is more than 70 billion times greater than a commercial 32-bit CPU.
Our prototype has a ternary RISC architecture with the following characteristics:

24 Trit Data BUS
12 Trit Address BUS
10x10cm CPU Board
Ternary Signal on external BUS
RISC Architecture with Ternary ISA
In addition to being interesting for the enormous amount of information and BUS Data of reduced dimensions, it can be applied to emerging fields of computer science, thanks to the fact of processing ternary data:

Artificial intelligence and deep learning (is the human brain ternary?)
Advanced and innovative calculation
Industrial and anthropomorphic robotics
Research on algorithms


On Sunday 5 May 2019, Cesare di Mauro will present a talk on the creation of a ternary assembler at the PyCon in Florence, Italy.
Cesare Di Mauro is the creator of the Ternary ISA for 5500FP Ternary CPU board.
Ternary CPUs talk

board4_02.png [ 424.76 KiB | Viewed 262 times ]

"Ученье свет, а неученье — тьма. Дело мастера боится, и коль крестьянин не умеет сохою владеть — хлеб не родится." (С)
12 Sep 2021 05:59
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