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Wanting "play" with a KR1801VM2... 
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Junior

Joined: 19 Oct 2020 03:55
Posts: 1
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Hi, first post here! I hope not to go OT with this...

I've bought a KR1801VM2 CPU (it is on the way...) and I'm starting just now to try to "understand" this CPU.

I've seen your work on hackaday, but I miss a complete datasheet of this IC (and no, I don't speak Russian...).

I've found a partial datasheet here: https://bitbucket.org/cfib90/1801vm2/sr ... s/1801vm2/ but a lot of pages are missing (they should be about 166 pages).

The part I'm looking for is the "sequence" and timings for the DMA request "handshaking" (#DMR, #DMGO, #SACK) and if there is a sort of "Wait" signal to accommodate slow I/O (may be #SP1 and #SP2 pins???) and its timing.

As far as I've understood up to know the I/O is memory mapped only and there are two "pages" of 64Kwords (16bit wide) selected with the #SEL signal.
This second "hidden" page seems to be used for "special" purposes with a sort of exception handling (but I haven't any detail).

Regards.

J4F


19 Oct 2020 04:33
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Admin
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Joined: 09 Jan 2003 00:22
Posts: 18882
Location: Silicon Valley
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Actually VM2 is trying to resemble PDP-11 (more precisely LSI-11) as close as possible, so you can read PDP-11 docs 1st to see how it's supposed to work.

We have a topic with timings taken from official VM2 datasheet - see http://www.nedopc.org/forum/viewtopic.php?f=95&t=18777 (unfortunately it's all in Russian, so you need to use Goodle translate or something).

Basically PDP-11 doesn't have WAIT signal - all data bus communications are happening with a handshake so any peripheral must response in handshake in order data transfer to happen, so if it's slow then it simply response slower (but it can not be too slow otherwise on-board watchdog will send chip to trap).

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19 Oct 2020 12:30
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