Hi, first post here! I hope not to go OT with this...
I've bought a KR1801VM2 CPU (it is on the way...) and I'm starting just now to try to "understand" this CPU.
I've seen your work on hackaday, but I miss a complete datasheet of this IC (and no, I don't speak Russian...).
I've found a partial datasheet here:
https://bitbucket.org/cfib90/1801vm2/sr ... s/1801vm2/ but a lot of pages are missing (they should be about 166 pages).
The part I'm looking for is the "sequence" and timings for the DMA request "handshaking" (#DMR, #DMGO, #SACK) and if there is a sort of "Wait" signal to accommodate slow I/O (may be #SP1 and #SP2 pins???) and its timing.
As far as I've understood up to know the I/O is memory mapped only and there are two "pages" of 64Kwords (16bit wide) selected with the #SEL signal.
This second "hidden" page seems to be used for "special" purposes with a sort of exception handling (but I haven't any detail).
Regards.
J4F