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LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY Block1 IS
   PORT
   (
      ROMTD :  IN  STD_LOGIC;
      A14 :  IN  STD_LOGIC;
      A15 :  IN  STD_LOGIC;
      NASS :  IN  STD_LOGIC;
      IDP :  OUT  STD_LOGIC
   );
END Block1;

ARCHITECTURE bdf_type OF Block1 IS

SIGNAL   SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL   DFF_inst5 :  STD_LOGIC;
SIGNAL   SYNTHESIZED_WIRE_1 :  STD_LOGIC;
SIGNAL   SYNTHESIZED_WIRE_2 :  STD_LOGIC;

BEGIN

SYNTHESIZED_WIRE_0 <= NOT(ROMTD);

SYNTHESIZED_WIRE_2 <= NOT(SYNTHESIZED_WIRE_0 AND A14 AND A15);

SYNTHESIZED_WIRE_1 <= NOT(A14 AND A15);

IDP <= DFF_inst5 AND SYNTHESIZED_WIRE_1;

PROCESS(SYNTHESIZED_WIRE_2,NASS)
BEGIN
IF (NASS = '0') THEN
   DFF_inst5 <= '0';
ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_2)) THEN
   DFF_inst5 <= '1';
END IF;
END PROCESS;

END bdf_type;