Первый чип готов - это дешифратор адресов, порты (и старые, и новый - поддержаны старшие 4 бита порта #F7FF) и логика начального пуска 8085, которая по второму фетчу заменяет ROM на обычное распределение памяти - всё влезло в XC9536XL - даже ещё место осталось:
Code: Select all
----------------------------------------------------------------------------------
-- Company: nedoPC.org
-- Engineer: Shaos
--
-- Create Date: 17:33:05 12/01/2013
-- Design Name: orionix decoder
-- Module Name: main - Behavioral
-- Project Name: Orionix-2013
-- Target Devices: xc9436xl
-- Tool versions: ISE 14.7
-- Description: 1st CPLD chip for Orionix-2013
--
-- Dependencies:
--
-- Revision: 0.04
-- Revision 0.04 (12/12/2013) - Some names fixed
-- Revision 0.03 (12/11/2013) - Invered screen bits
-- Revision 0.02 (12/02/2013) - Fixed port F8xx
-- Revision 0.01 (12/01/2013) - File Created
-- Additional Comments:
-- This design is Public Domain
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( CLR : in STD_LOGIC;
AD0 : in STD_LOGIC;
AD1 : in STD_LOGIC;
AD2 : in STD_LOGIC;
AD3 : in STD_LOGIC;
AD4 : in STD_LOGIC;
AD5 : in STD_LOGIC;
AD6 : in STD_LOGIC;
AD7 : in STD_LOGIC;
A8 : in STD_LOGIC;
A9 : in STD_LOGIC;
A10 : in STD_LOGIC;
A11 : in STD_LOGIC;
A12 : in STD_LOGIC;
A13 : in STD_LOGIC;
A14 : in STD_LOGIC;
A15 : in STD_LOGIC;
ALE : in STD_LOGIC;
WR : in STD_LOGIC;
SAND : in STD_LOGIC;
CSRAM : out STD_LOGIC;
CSRAM2 : out STD_LOGIC;
CSROM2 : out STD_LOGIC;
VM0 : out STD_LOGIC;
VM1 : out STD_LOGIC;
VM2 : out STD_LOGIC;
IS0 : out STD_LOGIC;
IS1 : out STD_LOGIC;
WRP2 : out STD_LOGIC;
WRP4 : out STD_LOGIC;
CSKB : out STD_LOGIC;
CSD1 : out STD_LOGIC;
CSD2 : out STD_LOGIC;
CSEX : out STD_LOGIC);
end main;
architecture Behavioral of main is
signal FRS: STD_LOGIC;
signal SCN: STD_LOGIC;
signal A0: STD_LOGIC;
signal A1: STD_LOGIC;
signal A2: STD_LOGIC;
signal A3: STD_LOGIC;
signal A4: STD_LOGIC;
signal A5: STD_LOGIC;
signal A6: STD_LOGIC;
signal A7: STD_LOGIC;
signal DF0: STD_LOGIC;
signal DF1: STD_LOGIC;
signal ALM: STD_LOGIC;
signal DSB: STD_LOGIC;
begin
process (SCN,ALM,DSB,DF1,DF0,CLR,WR,AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,
A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15) is
begin
if CLR = '0' then
CSRAM <= '1';
CSRAM2 <= '1';
CSROM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
WRP2 <= '1';
WRP4 <= '1';
else
if SCN='1' then -- Show ROM everywhere
CSRAM <= '1';
CSRAM2 <= '1';
CSROM2 <= '0';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
WRP2 <= '1';
WRP4 <= '1';
elsif ALM='1' then -- Show shadow memory
CSRAM <= '0';
CSRAM2 <= '1';
CSROM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
WRP2 <= '1';
WRP4 <= '1';
elsif A15='1' and A14='1' and A13='1' and A12='1' then -- Fxxx
CSRAM <= '1';
if A11='1' then -- F800..FFFF
CSRAM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
if WR='0' then -- Writing to the ports (see other process for actual writing)
CSROM2 <= '1';
if A10='0' and A9='0' and A8='1' then -- Write to F9xx (external register)
WRP2 <= '0';
else
WRP2 <= '1';
end if;
if A10='0' and A9='1' and A8='1' then -- Write to FBxx (external register)
WRP4 <= '0';
else
WRP4 <= '1';
end if;
else -- Reading from the ROM
CSROM2 <= '0';
WRP2 <= '1';
WRP4 <= '1';
end if;
else -- F000..F7FF
if A0='1' and A1='1' and A2='1' and A3='1' and A4='1' and A5='1' and A6='1' and A7='1' then -- F7FF
if DSB='0' then -- F7FF enabled
CSRAM2 <= '0';
CSEX <= '1';
else -- F7FF disabled
if DF1='1' then -- extension slot disabled
CSRAM2 <= '0';
CSEX <= '1';
else -- extension slot enabled
CSRAM2 <= '1';
CSEX <= '0';
end if;
end if;
CSROM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
WRP2 <= '1';
WRP4 <= '1';
else -- F000..F7FE
if A10='1' then -- F400..F7FE
CSROM2 <= '1';
WRP2 <= '1';
WRP4 <= '1';
if A9='0' and A8='0' then -- F4xx
if DF1='1' and DF0='1' then -- keyboard disabled (11)
CSRAM2 <= '0';
CSKB <= '1';
elsif DF1='0' and DF0='0' then -- keyboard enabled (00)
CSRAM2 <= '1';
CSKB <= '0';
else -- keyboard enabled only in four addresses (01,10)
if A7='0' and A6='0' and A5='0' and A4='0' and A3='0' and A2='0' then
CSRAM2 <= '1';
CSKB <= '0';
else -- otherwise it's RAM
CSRAM2 <= '0';
CSKB <= '1';
end if;
end if;
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
elsif A9='0' and A8='1' then -- F5xx
if DF1='1' then -- device disabled (10,11)
CSRAM2 <= '0';
CSD1 <= '1';
elsif DF0='0' then -- device enabled (00)
CSRAM2 <= '1';
CSD1 <= '0';
else -- device enabled only in four addresses (01)
if A7='0' and A6='0' and A5='0' and A4='0' and A3='0' and A2='0' then
CSRAM2 <= '1';
CSD1 <= '0';
else
CSRAM2 <= '0';
CSD1 <= '1';
end if;
end if;
CSKB <= '1';
CSD2 <= '1';
CSEX <= '1';
elsif A9='1' and A8='0' then -- F6xx
if DF1='1' then -- device disabled (10,11)
CSRAM2 <= '0';
CSD2 <= '1';
elsif DF0='0' then -- device enabled (00)
CSRAM2 <= '1';
CSD2 <= '0';
else -- device enabled only in four addresses (01)
if A7='0' and A6='0' and A5='0' and A4='0' and A3='0' and A2='0' then
CSRAM2 <= '1';
CSD2 <= '0';
else
CSRAM2 <= '0';
CSD2 <= '1';
end if;
end if;
CSKB <= '1';
CSD1 <= '1';
CSEX <= '1';
else -- F7xx
if DF1='1' then -- extension slot disabled (10,11)
CSRAM2 <= '0';
CSEX <= '1';
else -- extension slot enabled (00,01)
CSRAM2 <= '1';
CSEX <= '0';
end if;
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
end if;
else -- F000..F3FF
CSRAM2 <= '0';
CSROM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
WRP2 <= '1';
WRP4 <= '1';
end if;
end if;
end if;
else -- 0000..EFFF
CSRAM <= '0';
CSRAM2 <= '1';
CSROM2 <= '1';
CSKB <= '1';
CSD1 <= '1';
CSD2 <= '1';
CSEX <= '1';
WRP2 <= '1';
WRP4 <= '1';
end if;
end if;
end process;
process (ALE,AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7) is
begin
if ALE'event and ALE='0' then -- falling edge
A0 <= AD0;
A1 <= AD1;
A2 <= AD2;
A3 <= AD3;
A4 <= AD4;
A5 <= AD5;
A6 <= AD6;
A7 <= AD7;
end if;
end process;
process (CLR,WR,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0,ALM,DSB) is
begin
if CLR = '0' then
VM0 <= '0';
VM1 <= '0';
VM2 <= '0';
IS0 <= '1';
IS1 <= '1';
DF0 <= '0';
DF1 <= '0';
ALM <= '0';
DSB <= '0';
elsif WR'event and WR='1' then -- rising edge of WR
if A15='1' and A14='1' and A13='1' and A12='1' and A11='0' and A10='1' and A9='1' and A8='1' and A7='1' and A6='1' and A5='1' and A4='1' and A3='1' and A2='1' and A1='1' and A0='1' then -- Write to F7FF
if ALM='0' and DSB='0' then -- F7FF enabled
DF0 <= AD4;
DF1 <= AD5;
ALM <= AD6;
DSB <= AD7;
end if;
elsif A15='1' and A14='1' and A13='1' and A12='1' and A11='1' then -- >=F800
if ALM='0' and A10='0' and A9='0' and A8='0' then -- Write to F8xx
VM0 <= AD0;
VM1 <= AD1;
VM2 <= AD2;
elsif ALM='0' and A10='0' and A9='1' and A8='0' then -- Write to FAxx
if AD0='0' then
IS0 <= '1';
else
IS0 <= '0';
end if;
if AD1='0' then
IS1 <= '1';
else
IS1 <= '0';
end if;
elsif A10='1' and A9='1' and A8='1' then -- Write to FFxx
if ALM='1' then -- Hide shadow memory
ALM <= '0';
end if;
if DSB='1' then -- Enable port F7FF
DSB <= '0';
end if;
end if;
end if;
end if;
end process;
process (CLR,SAND,FRS,SCN) is
begin
if CLR = '0' then -- reset
FRS <= '1';
SCN <= '1';
elsif SAND'event AND SAND='1' then -- rising edge
if FRS='1' then -- 1st step
FRS <= '0';
elsif SCN='1' then -- 2nd step
SCN <= '0';
end if;
end if;
end process;
end Behavioral;
Xilinx ISE превратил этот VHDL код вот в такое:
Code: Select all
********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$24_INV$105 <= (A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND A0 AND A1);
FDCPE_A0: FDCPE port map (A0,AD0,NOT ALE,'0','0');
FDCPE_A1: FDCPE port map (A1,AD1,NOT ALE,'0','0');
FDCPE_A2: FDCPE port map (A2,AD2,NOT ALE,'0','0');
FDCPE_A3: FDCPE port map (A3,AD3,NOT ALE,'0','0');
FDCPE_A4: FDCPE port map (A4,AD4,NOT ALE,'0','0');
FDCPE_A5: FDCPE port map (A5,AD5,NOT ALE,'0','0');
FDCPE_A6: FDCPE port map (A6,AD6,NOT ALE,'0','0');
FDCPE_A7: FDCPE port map (A7,AD7,NOT ALE,'0','0');
FTCPE_ALM: FTCPE port map (ALM,ALM_T,WR,NOT CLR,'0');
ALM_T <= ((A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND ALM AND
A11)
OR (AD6 AND A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND
NOT ALM AND NOT DSB AND NOT A11 AND A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND
A0 AND A1));
CSD1 <= NOT (((NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A7)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A0)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A1)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND NOT A6 AND
NOT A7)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A2)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A3)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A4)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A5)
OR (NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A6)));
CSD2 <= NOT (((A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A7)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A0)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A1)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND NOT A6 AND
NOT A7)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A2)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A3)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A4)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A5)
OR (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A6)));
CSEX <= NOT (((A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A7)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A0)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A1)
OR (A15 AND A14 AND A13 AND A12 AND CLR AND NOT ALM AND NOT DF1 AND
DSB AND NOT A11 AND NOT SCN AND A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND
A0 AND A1)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A2)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A3)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A4)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A5)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A6)));
CSKB <= NOT (((NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A7)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A0)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A1)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT A11 AND NOT SCN AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND NOT A6 AND
NOT A7)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND NOT A6 AND
NOT A7)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A2)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A3)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A4)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A5)
OR (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND CLR AND
NOT ALM AND NOT DF1 AND NOT DF0 AND NOT A11 AND NOT SCN AND NOT A6)));
CSRAM <= ((NOT CLR)
OR (SCN)
OR (A15 AND A14 AND A13 AND A12 AND NOT ALM));
CSRAM2 <= ((NOT A15)
OR (NOT A14)
OR (NOT A13)
OR (NOT A12)
OR (NOT CLR)
OR (NOT DF1 AND DSB AND $OpTx$$OpTx$FX_DC$24_INV$105)
OR (A10 AND NOT DF1 AND NOT DF0 AND NOT $OpTx$$OpTx$FX_DC$24_INV$105)
OR (A9 AND A8 AND A10 AND NOT DF1 AND
NOT $OpTx$$OpTx$FX_DC$24_INV$105)
OR (A10 AND NOT DF1 AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND NOT A6 AND NOT A7)
OR (NOT A9 AND NOT A8 AND A10 AND NOT DF0 AND NOT A2 AND NOT A3 AND NOT A4 AND NOT A5 AND
NOT A6 AND NOT A7)
OR (ALM)
OR (A11)
OR (SCN));
CSROM2 <= NOT (((CLR AND SCN)
OR (A15 AND A14 AND A13 AND A12 AND WR AND CLR AND NOT ALM AND
A11)));
FDCPE_DF0: FDCPE port map (DF0,AD4,WR,NOT CLR,'0',DF0_CE);
DF0_CE <= (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND NOT ALM AND
NOT DSB AND NOT A11 AND A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND A0 AND
A1);
FDCPE_DF1: FDCPE port map (DF1,AD5,WR,NOT CLR,'0',DF1_CE);
DF1_CE <= (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND NOT ALM AND
NOT DSB AND NOT A11 AND A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND A0 AND
A1);
FTCPE_DSB: FTCPE port map (DSB,DSB_T,WR,NOT CLR,'0');
DSB_T <= ((A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND DSB AND
A11)
OR (A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND A10 AND AD7 AND
NOT ALM AND NOT DSB AND NOT A11 AND A2 AND A3 AND A4 AND A5 AND A6 AND A7 AND
A0 AND A1));
FDCPE_FRS: FDCPE port map (FRS,'0',SAND,'0',NOT CLR,FRS);
FDCPE_IS0: FDCPE port map (IS0,NOT AD0,WR,'0',NOT CLR,IS0_CE);
IS0_CE <= (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT ALM AND
A11);
FDCPE_IS1: FDCPE port map (IS1,NOT AD1,WR,'0',NOT CLR,IS1_CE);
IS1_CE <= (A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT ALM AND
A11);
FDCPE_SCN: FDCPE port map (SCN,'0',SAND,'0',NOT CLR,SCN_CE);
SCN_CE <= (SCN AND NOT FRS);
FDCPE_VM0: FDCPE port map (VM0,AD0,WR,NOT CLR,'0',VM0_CE);
VM0_CE <= (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT ALM AND
A11);
FDCPE_VM1: FDCPE port map (VM1,AD1,WR,NOT CLR,'0',VM1_CE);
VM1_CE <= (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT ALM AND
A11);
FDCPE_VM2: FDCPE port map (VM2,AD2,WR,NOT CLR,'0',VM2_CE);
VM2_CE <= (NOT A9 AND NOT A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT ALM AND
A11);
WRP2 <= NOT ((NOT A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT WR AND
CLR AND NOT ALM AND A11 AND NOT SCN));
WRP4 <= NOT ((A9 AND A8 AND A15 AND A14 AND A13 AND A12 AND NOT A10 AND NOT WR AND
CLR AND NOT ALM AND A11 AND NOT SCN));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
Статистика:
Code: Select all
Fitter Report
Design Name: main Date: 12-12-2013, 2:09AM
Device Used: XC9536XL-10-PC44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
29 /36 ( 81%) 86 /180 ( 48%) 60 /108 ( 56%) 19 /36 ( 53%) 34 /34 (100%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 35/90 17/17*
FB2 11/18 29/54 51/90 17/17*
----- ----- ----- -----
29/36 60/108 86/180 34/34
* - Resource is exhausted
** Global Control Resources **
Signal 'ALE' mapped onto global clock net GCK1.
Signal 'SAND' mapped onto global clock net GCK2.
Signal 'WR' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'CLR' mapped onto global set/reset net GSR.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 16 16 | I/O : 28 28
Output : 14 14 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 2 2
GCK : 3 3 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 34 34
Распределение ног:
Code: Select all
****************************** Device Pin Out *****************************
Device : XC9536XL-10-PC44
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
| 7 39 |
| 8 38 |
| 9 37 |
| 10 36 |
| 11 XC9536XL-10-PC44 35 |
| 12 34 |
| 13 33 |
| 14 32 |
| 15 31 |
| 16 30 |
| 17 29 |
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 CSRAM2 23 GND
2 AD7 24 WRP4
3 CSD2 25 AD3
4 IS0 26 AD4
5 ALE 27 AD2
6 SAND 28 CSROM2
7 WR 29 A13
8 AD5 30 TDO
9 IS1 31 GND
10 GND 32 VCC
11 A15 33 CSRAM
12 VM0 34 CSEX
13 AD6 35 AD0
14 VM1 36 A11
15 TDI 37 A12
16 TMS 38 CSD1
17 TCK 39 CLR
18 A9 40 AD1
19 VM2 41 VCC
20 A8 42 A10
21 VCC 43 CSKB
22 WRP2 44 A14
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
