Wanting "play" with a KR1801VM2...

[Just4Fun]

Here the connections of the VM2 CPU during the last tests:

KR1801VM2 test.jpg

The /AR pin is connected with the /SYNC and the /RPLY pin is fixed to "1" (but isn't a problem to reach the first part of the CPU "starting sequence" when both /SEL and /DIN are LOW for the "unaddressed reading").
But in my results both /SEL and /DIN are always at HIGH.
Another erratic behavior is the /INIT signal that is supposed to be LOW when both /DCLO and /ACLO are LOW at the beginning of the reset sequence.

In the last tests I've detached the "Shield" from the MCU board to follow your scheme with 2k7 pullups, but with the same result.

20220917_125759B.jpg

[Mixa64]

Hi there.
You may want to measure negative substrate bias voltage. At the short sides of the case, e.g. between pins 20 & 21, you see small metal exit points. The voltage there should be somewhere -2.6 .. -2.7 V
Probably that's OK in your case, otherwise the case heats extremely.

The simplest way to check ACLO DCLO to INIT path:
1, 20 to GND
40 to Vcc
16 (CLCI) to GND
25,26 interconnect
27 2.7k pullup to Vcc
Then, switching 25,26 via series R (the same value of 2.7k is ok) between GND and Vcc you see that voltage @ 27 follows input level @ 25,26
If 25,26 are toggled when 16 is Vcc, there's no effect on pin 27. Only negative edge transition @ 16 makes output @ 27 to change, and next positive edge latches the last level.

[Shaos]

Here the connections of the VM2 CPU during the last tests

Did you pull-up everything that should be pulled up? Everything that has letter P on my diagram - on your picture I see less resistors than it should be

Also your breadboard may not have power buses connected all the way through - check here for example:

[Just4Fun]

You may want to measure negative substrate bias voltage...

Hi Mixa64, thank you for the suggestions.

I've measured a substrate voltage of -2.65V (with a Vcc = 5.06V directly measured on the CPU pins) using the small metal point you said:

20221006_203358.jpg

About the INIT test, I've done as you said:

Power applied (1, 20 to GND and 40 to Vcc);
CLCI (16) to GND;
DCLO (26) and ACLO (25) connected together and with a 2k7 pullup to Vcc;
INIT (27) with a 2k7 pullup to Vcc (in parallel with a 4k7 pullup resistor to Vcc on the PCB);

but INIT is always fixed at Vcc, even when both pin 25 and 26 are to GND.
Also switching CLCI do not make follow on the INIT output pin (27) the value of pin 25 and 26 (connected together).

Did you pull-up everything that should be pulled up?

Yes, that photo misses a wire to Vcc I added later.
There are some pullups on the red board:

WRQ (10) and INIT (27) have a 4k7 pullup to Vcc on the PCB;
SACK (13), DMR (12), VIRQ (28), HALT (29), EVNT (30) have 10k pullups to Vcc on the PCB;
WAKI (11) is connected to GND on the PCB (with a jumper);
AR (23) is connected to SYNC (21) on the PCB (with a jumper).

I've checked their levels and are at Vcc (with the only exception of WAKI of course), so those pullups are fine.

The only pin that is working is CLCO that outputs the CLCI input clock divided by 2. All the other pins seem fixed whatever you do.

[Shaos]

Then try to purchase another VM2

[Just4Fun]

Yes of course!
Unfortunately in "this period" it's impossible to find one, so I've to wait for "better times"...

[Shaos]

Yes of course!
Unfortunately in "this period" it's impossible to find one, so I've to wait for "better times"...

I have a few - I think I can send you 100% working one from US

[Just4Fun]

Thank you very much! It would be great...

Of course I'll pay for the shipment and the CPU.

I'll send a PM to you.

[Just4Fun]

Hi all,
thanks to Shaos now I'm on the road again...

I'm currently waiting for the KR1801VM2 Application Board (APB) 4-layer PCB from the fab. Here the final rendering:

A291221.jpg

It is a self powered CPU board to be used with the Studio 68 FPGA board (see ahead).

I've also prepared another board, the KR1801VM2 Blinking Leds (BLL), but this one will came later:

A050922.jpg

These boards will be used together with the Studio 68, an FPGA board I made for "retro experiments".
The final result will be something similar to what I've already done with a Z80 (in the photo the Z80 Application Board + Z80 Blinking Leds + Studio 68):

20221207_200254B.jpg

We'll see...

[Shaos]

Looks great

[Just4Fun]

First "hello world" test with the KR1801VM2 Application Board (APB) + Studio 68 :

20230119_191948_b.jpg

KR1801VM2_hello.jpg

Code: Select all

000000                             ;
000000                             ; Hello World for the KR1801VM2 ABP (A291221) + Studio 68 (A100821) using M4K RAM blocks
000000                             ;
000000                             ; Required: H020123 VHDL (FPGA logic) and S160123 (STM32 side)
000000                             ;
000000                             ; Assembled with AsmPDP.exe (windows) assembler (http://mdfs.net/Software/PDP11/Assembler)
000000                             ; (NOTE: Hex values must be uppercase; i.e &0A is valid, &0a not!!!)
000000                             ;
000000                             
000000                             
000000                             ; H020123 equates
000000                             IO_STATUS:      equ         &FFF0   ; IO Status Register (IR0 read only)
000000                             SER_TX:         equ         &FFF2   ; Serial Tx IO Register (OR1 write only)
000000                             SER_RX:         equ         &FFF2   ; Serial Rx IO Register (IR1 read only)
000000                             MAX_RAM:        equ         &2FFE   ; Max allowed RAM word address (RAM is 6.144 words wide)
000000                             
000000                             ; Common chars
000000                             eos:            equ         &00     ; End of string
000000                             cr:             equ         &0D     ; Carriage return
000000                             lf:             equ         &0A     ; Line feed
000000                             
000000                                     org     0
000000                             ; Boot vecctors
000000 000144                              equw    start               ; PC content loaded at boot
000002 000340                              equw    &00E0               ; PSW content loaded at boot
000004                             
000144                                     org     100
000144                             start:
000144 012706 027764                       mov     #stack,r6           ; Initialize the SP
000150 010701                              mov     pc,r1
000152 062701 000044                       add     #msg-$,r1           ; calculate address of 'hello'
000156                             
000156                             loop:
000156 112100                              movb    (r1)+,r0            ; get byte from r1, inc r1
000160 001403                              beq     end                 ; exit if final byte
000162 004767 000004                       jsr     pc,putc             ; send current character (R0 low)
000166 000773                              br      loop                ; loop back
000170                             
000170                             end:
000170 000765                              br      start               ; loop forever
000172                             
000172                             ;
000172                             ; Print a charcter on R0 low
000172                             ;
000172                             putc: 
000172 012702 177760                       mov     #IO_STATUS,r2       ; R2 = address of the IO_STATUS I/O register
000176                             waitTxRdy:
000176 111203                              movb    (r2),r3             ; R3 = IO_STATUS content
000200 132703 000040                       bitb    #&20,r3             ; Serial Tx ready (Z=0)?
000204 001774                              beq     waitTxRdy           ; No, jump
000206 012702 177762                       mov     #SER_TX,r2          ; R2 = address of the SER_TX I/O register
000212 110012                              movb    r0,(r2)             ; Write current char to the SER_TX register
000214 000207                              rts     pc                  ; Return
000216                             
000216                             msg:
000216 110 145 154 154 157 040 167 157
       162 154 144 040 146 162 157 155
       040 164 150 145 040 113 122 061
       070 060 061 126 115 062 040 103
       120 125 041 015 012 000             equs "Hello world from the KR1801VM2 CPU!", cr, lf, eos
000264                                     align
000264                             
027764                                     org     MAX_RAM - 10
027764                                     align
027764                             stack:
Errors: 0

In this first test I've used the SRAM inside the FPGA (M4K RAM blocks) for simplicity.
This way I can assemble a program and "embed" the resulting binary directly into the FPGA bitstream, so the RAM is automatically preset with the binary program ready to run.

[Shaos]

Cool!!! Congrats

[Just4Fun]

The original PDP-11 paper tape BASIC running on my "Frankenstein" PDP11/03 with a soviet KR1801VM12 CPU...

Screenshot from 2023-02-23 20-47-29.png

20230223_205538.resized.jpg

[Shaos]

Wow! Really?
Can you share binary?