TRIMUX - two ternary multiplexers on one PCB

[Shaos]

My new board - two ternary multiplexers on one triangle-shaped PCB - TRIMUX ( see http://www.trimux.com ):



Schematics are very simple:



IC1,IC2: DG403 (DIP16)
C1,C2,C3,C4: 0.1uF (tantalum)
JP1,JP2: right-angle 5-pin headers
JP3: right-angle 3-pin header

Connector JP1:
1) S1 - select input of the 1st ternary multiplexer
2) N1 - connected to C1 (common signal of the 1st ternary multiplexer) if S1=N ("negative" or -5V)
3) O1 - connected to C1 (common signal of the 1st ternary multiplexer) if S1=O ("zero" or 0V)
4) P1 - connected to C1 (common signal of the 1st ternary multiplexer) if S1=P ("positive" or +5V)
5) C1 - common signal of the 1st ternary multiplexer

Connector JP2:
1) S2 - select input of the 2nd ternary multiplexer
2) N2 - connected to C2 (common signal of the 2nd ternary multiplexer) if S2=N ("negative" or -5V)
3) O2 - connected to C2 (common signal of the 2nd ternary multiplexer) if S2=O ("zero" or 0V)
4) P2 - connected to C2 (common signal of the 2nd ternary multiplexer) if S2=P ("positive" or +5V)
5) C2 - common signal of the 2nd ternary multiplexer

Connector JP3:
1) V-NEG - negative voltage (typically -5V)
2) GND - ground wire
3) V-POS - positive voltage (typically +5V)

P.S. Eagle design released under GPL v3: http://www.nedopc.org/ternary/trimux-eagle.zip (296K)

P.P.S. Also I developed software package for automatic design of ternary schemes based on DG403:
viewtopic.php?t=172

P.P.P.S. Assembled TRIMUX:


Components: http://www.mouser.com/ProjectManager/Pr ... 38f4dfdfd8

Since 2015 it's availabe for purchase from Tindie marketplace:

https://www.tindie.com/products/TRC/tri ... ltiplexer/

[Shaos]

It is based on my recent idea of using analog switches DG403 in ternary schematics (July 2010):



Ternary signal may be connected to positive voltage (+1 or P), negative voltage (-1 or N) or ground (0 or O). By connecting logic voltage pins of DG403 (Vl and GND) to upper or lower part of full range of analog voltage (between V- and V+) we may get two different types of basic ternary elements - E12 (Vl=Ground, GND=Negative) and E21 (Vl=Positive, GND=Ground). Each DG403 may have two E12 or two E21 elements. One E12 and one E21 may be connected together to create ternary multiplexer (MUX) or universal ternary element. So two DG403 may create two universal ternary elements (ternary multiplexers/demultiplexers)

As you can see on lower part of the scheme in order to get ternary inverter we need to connect N2 to +5V, O2 to 0V and P2 to -5V and after that S2 will be input of ternary inverter and C2 will be output.

Later I plan to design simplified ternary multiplexer just for E12 or E21 elements (it will consist of only one DG403).

[jay4th]

Have you tested this circuit? I am concerned after reading a note on the datasheet (see http://www.vishay.com/docs/70049/dg401.pdf )

Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

My concern is prompted by ignorance of CMOS in part. I am looking at the circuit diagram of the chip, imagining a DG403 wired so that VL = 0V, GND = -5V, V+ = +5V, and V- = -5V. Suppose Vin = +4.9 V. That is much larger than VL, and there are no clamping diodes. Will the FET be happy with the gate at a much higher voltage than either source or drain? Since in a design the Vin will be subject to switching transients and inductive/capictive generated voltage spikes, you could easily see Vin not only above VL (by design) but well above V+.

Would things be better if the system were redesigned to have V+ = +15, V- = -15, and VL either +5 or 0, and GND either 0 or -5? Then the 'over voltage' or similar 'under voltage' situation is proportionally smaller, and hopefully small enough to keep from putting something delicate into a very reverse-biased position. I need a better CMOS education...

Then I need help understanding this: In the described situation, with Vin well over VL, is the normally open switch closed or open? I suspect closed, though I would wish it were only closed for V-/2 <= Vin <= V+/2.

[Shaos]

Thanks for comment!

According to datasheet it looks OK to have Vin higher than VL (or lower than GND), because it isn't forbidden directly.

When I tested this schematics in August (in that time I used SOIC DG403s), I got this results:

[jay4th]

Just for fun I made gschem symbols for use of DG403 and DG405 used in the way you have designed. Then I used gschem and pcb to lay out a 1 trit and 3 trit ripple carry adder printed circuit boards. The 1 trit is about 1inch x 5.5inches so up to 4 trits will fit on one 100x160mm Euro card using through-hole parts. About twice as many using surface mount. Unfortunately I can't get a nice two layer layout, so I went ahead and did 4 layer. Have schematics for a tri-flop (more a tri-latch actually), but not sure if it would work or not.

However, these devices are so slow (c. 100ns) that I wouldn't want to go much past 4 trits in a ripple carry design. I am looking at a carry-select design, I'll have some designs if you want. Not sure though that any design calling for 432 instances of any part is very practical, but it's fun to dream of building a 12 trit machine.

If I win the lottery (ha!) maybe I'll build a silicon implementation of Setun. It's not too big a machine by modern standards... Though 18 trits... even using surface mount parts that won't fit on a single 100x160mm Eurocard! Maybe a 6U card though... Think I'll go design a 12 trit ALU, see if I can keep the addition time under 500NS.

[Shaos]

It is very interesting to see what you created! Do you plan to publish it somehow on the Internet?
P.S. Did you try yet my automatic design package DDT? I'm still struggling with visualization...

[jay4th]

I would be happy to share what I have done, and make it available under GPL 2. However, I have no way to host files. PM me and I can email you what I have... still jamming the bypass capacitors in. 36 chips in 100x160mm is tight, fitting 48 is just barely possible I think.

No, I didn't try DDT. I looked at the source, can't figure out what it's doing with just a quick glance. I read the paper about the 3trit transistor level trinary (proof of concept) computer built as a student project. Kinda thinking about designing an implementation of the architecture using DG403 and 405 chips.

It seems like a job for Lisp to me -- searching for a minimal circuit. It also seems like a hard problem, combinatorial explosion and all. Does DDT do an exhaustive search?

The particular circuit, full adder, is pretty obvious to me how to implement with 12 chips given their design. The "E21" and "E12" functions leap out of the page as you draw the schematic. Btw, why do you call them E21 and E12, where can I find the names of the various 'gates' or functions people write about? All the trinary web sites seem to have died. Anyway, I replaced regular 2 half chip muxes with single (half chip) switches at those points.

I have this strong suspicion that the carry circuit can be optimized further, but fooling around with pencil and paper, and with gschem I haven't been able to do better than 6 chips yet.

[Shaos]

You can see E12 on the left and E21 on the right of this picture. I came up with these names, because E12 (element "one-two") may be used to implement any unary ternary function with truth-table XYY and E21 (element "two-one") may be used to implement any unary ternary function with truth-table XXY.

In DDT I basically programmed algorithm of creating ternary schematics that I used manually "with pencil and paper". So yes - it is definitely obvious, but can save some time

Also DDT produces output in form of C-source that can be directly used in simulation, but this C-source also represents schematics itself with possibility of visualization. Unfortunately DDT doesn't produce optimal solution (at least not for all problems) - in order to do so I need to implement truth tables permutations on internal levels also.

To see what we have computed already check this automatically translated page:
http://babelfish.yahoo.com/translate_ur ... =Translate
(results started on the second page)

[Shaos]

1st bunch of PCBs are received:

[jay4th]

Very cool! I look forward to photos of populated boards, and reports from the lab-bench.

[Shaos]

Very cool! I look forward to photos of populated boards, and reports from the lab-bench.

Problem is that boards are unfinished - they have bare copper on pads instead of soldering or silver or something...

[jay4th]

I noticed that, usually the copper on pcb's is tinned to make soldering easier. I thought it was a little strange to see copper and not silvery/white metal.

[Shaos]

I noticed that, usually the copper on pcb's is tinned to make soldering easier. I thought it was a little strange to see copper and not silvery/white metal.

I sent them a question...

[Shaos]

I noticed that, usually the copper on pcb's is tinned to make soldering easier. I thought it was a little strange to see copper and not silvery/white metal.

I sent them a question...

OK, BatchPCB said that it's normal now - if it's OSP (Organic Solderability Preservatives) then it defends copper not more than half a year and could be destroyed by heat higher that 150 degree of Celsius...

[Shaos]

1st board was assembled and tested - it's working



When V-NEG=-4.4V and V-POS=+4.4V TRIMUX has thresholds at -3.1V and +1.6V (around second threshold there is a short range of voltage when one switch is already opened, but second is not yet closed). Later I will test it on voltages +5V and -5V.