Realizing a ternary microprocessor with CPLDs?

[eudoxie]

I've been thinking, since it's possible to realize simpler microprocessors with CPLD:s (or FPGA:s), wouldn't it be theoretically possible to realize a ternary microprocessor that way as well? I know for a fact that people have implemented the 6502 microprocessor on a FPGA, so the level of complexity should be doable, no?

Has anyone tried anything like this?

[Mac Buster]

I've been thinking, since it's possible to realize simpler microprocessors with CPLD:s (or FPGA:s), wouldn't it be theoretically possible to realize a ternary microprocessor that way as well?

Well, I know some people claimed that they're working on someting like that, but I never heard from them anymore

But I have no doubt that the thing could be released in FPGA.

[Shaos]

I do not see any problems to do this on CPLD or FPGA
External interface could be 2 binary pins for each ternary signal

[cr0acker]

Well of cource it can be done. I would raher do it in other way. It would not be so expansive to make in real silicon with mosix academic program. The CPU can be made in two chips the first one analog(with BiCMOS process) will be the core of ternary CPU, and the second chip(analog-digital), system controller, will inteface existing binary logic chips(like ram and rom) to ternary core. My real concern is, that it is really hard to use modern cpu design technics(like microcode, external execution units, etc) to build ternary chip.

[cr0acker]

You can use FPAA's.
http://en.wikipedia.org/wiki/FPAA
Two for the core and one for the binary bus translators.

[Shaos]

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