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nedoPC - 1 / Core

Open source design of nedoRISC processor was started on http://nedopc.org/forum at the end of 2009 as an example of a 16-bit RISC processor with Harvard architecture (separate data and instruction memory). Data has 16-bit width and code has 20-bit width. ALU is capable to compute different operations for 2 different bytes of the word. Also core has Supervisor? mode that may be ignored by user if only user mode applications are developed.

In user mode there are 16 directly addressable 16-bit registers R0...R15?. Register R0? is always 0 if used as source and nothing if used as destination. Registers R1-R4? are global registers that always stay in place. Registers R5-R13? are local registers that may be shifted down on CALL and up on RET instructions by number from 3-bit field CUR? from flags register R14 (so physically it is more than 16 registers, but actual number does not matter in user mode). Register R14 is set of Flags (S?, Z?, V?, C?, H?, O?, PCHI?, PAR?, CUR?) and register R15? is 16 lower bits of program counter PC? (4 higher bits are available from flags PCHI?).

Instruction set (4 bits of instruction code then 20 bits of arguments):

  • 0000 (0) - OP (arithmetic or logic operation with higher and lower bytes of two registers with storing result in destination register);
  • 0001 (1) - JUMP (jump to 20-bit address of instruction memory);
  • 0010 (2) - CALL (call subroutine from 20-bit address of instruction memory);
  • 0011 (3) - RET (return from subroutine and store 16-bit data to specified register);
  • 0100 (4) - LOAD? (load data from memory to register using 16-bit immediate address and 4-bit from flags PCHI?);
  • 0101 (5) - SAVE? (save data from register to memory using 16-bit immediate address and 4-bit from flags PCHI?);
  • 0110 (6) - INIT? (initialize register by immediate 16-bit number);
  • 0111 (7) - COPY? (copy part of immediate byte to register with offset);
  • 1000 (8) - CLR? (clear bit of register and store immediate byte to other register);
  • 1001 (9) - SET? (set bit of register and store immediate byte to other register);
  • 1010 (A) - SKIP0? (check bit in register, skip next instruction if 0 and store immediate byte to other register);
  • 1011 (B) - SKIP1? (check bit in register, skip next instruction if 1 and store immediate byte to other register);
  • 1100 (C) - ILOAD? (indirect load register using 2 next registers as address with immediate offset);
  • 1101 (D) - ISAVE? (indirect save register using 2 next registers as address with immediate offset);
  • 1110 (E) - TEST? (test bits by immediate 16-bit mask and set/clear flag Z);
  • 1111 (F) - EXT? (future extensions).
Page last modified on November 20, 2015, at 06:22 PM

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