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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Наконец-то сделал что-то на VHDL в Xilinx ISE 10.1 (проапгрейдившись до 10.1.03) под своим линуксом (Slackware 12.2). Есть проблемы - иногда падает в Segmentation Fault (в особенности если переключаться между окнами и быстро тыкать мышой куда-нибудь в юзер-интерфейс) и Floorplan IO не запускается (трюки подчерпнутые из инета не помогли) - пришлось ноги вручную прописывать в UCF-файле (хорошо, что он текстовый). Подробности тут: http://www.nedopc.org/forum/viewtopic.php?t=9135
Last edited by Shaos on 01 Dec 2013 14:33, edited 1 time in total.
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07 Sep 2009 09:11 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Благодаря опенсорсникам отпала необходимость запускать бинарный модуль ядра (который требует старого ядра и должен запускаться под рутом - что опасно), чтобы прошивать чипы от Xilinx - подробности читать тут:
http://www.rmdir.de/~michael/xilinx/
Вместо модуля ядра предлагается делать прелоад из под обычного юзера некоей либы (есть исходники), которая работает с LPT и USB шнурками для Xilinx представляя данные в ожидаемом формате и ихняя среда разработки это хавает!
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29 Dec 2009 20:07 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Ставлю Xilinx ISE 14.7 на Debian Linux 7.1 (wheezy) - с ходу ./xsetup не запустился (точнее запустился, но не показал никаких опций для установки), пришлось запускать bin/lin/xsetup - пока ставится дальше (будет занимать порядка 15 гигов)
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01 Dec 2013 14:38 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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В результате заняло 18 гигов
Пошёл кланяться за бесплатной лицензией...
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01 Dec 2013 15:10 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Вроде заработало - очередная моя попытка подружиться с Xilinx:
http://www.nedopc.org/forum/viewtopic.php?t=10484
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01 Dec 2013 20:21 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Чего-то симулятор отказывается запускаться в линухе - придётся свой симулятор городить - на сях
P.S. Нашёл тут в онлайне описалово зайлинксовских CPLD блоков (слегка устаревшее):
http://www.cs.indiana.edu/hmg/le/projec ... fc_scm.htm
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03 Dec 2013 19:16 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Как-то так оно будет:
| | | | Code: /* xemul.h - Emulation of X output (03-DEC-2013) A.A.Shabarshin <ashabarshin@gmail.com> */
#ifndef __XEMUL_H #define __XEMUL_H
#define _T_ (-1) /* TRUE */ #define _F_ (0) /* FALSE */ #define _R_EDGE (1) /* RISING EDGE */ #define _F_EDGE (-2) /* FALLING EDGE */
#define AND && #define OR || #define NOT ~
#define BIT(X) ((X)?1:0) #define CHR(X) ((X>0)?'^':((!X)?'0':((X==_T_)?'1':((X==_F_EDGE)?'v':'?'))))
/*
FDCPE(Q,D,C,CLR,PRE,CE):
CLR PRE CE D C Q ----------------- 1 X X X X 0 0 1 X X X 1 0 0 0 X X stored 0 0 1 D ^ D
*/
#define FDCPE(Q,D,C,R,S,E) ((R)?_F_:((S)?_T_:(((E)&&(C)>0)?((D)?_T_:_F_):((Q)?_T_:_F_))))
/*
FTCPE(Q,T,C,CLR,PRE,CE):
CLR PRE CE T C Q ----------------- 1 X X X X 0 0 1 X X X 1 0 0 0 X X stored 0 0 1 0 X stored 0 0 1 1 ^ toggle
*/
#define FTCPE(Q,T,C,R,S,E) ((R)?_F_:((S)?_T_:(((E)&&(T)&&(C)>0)?((Q)?_F_:_T_):((Q)?_T_:_F_))))
/*
LDCP(Q,D,G,CLR,PRE):
CLR PRE G D Q -------------- 1 X X X 0 0 1 X X 1 0 0 1 D D 0 0 0 X stored
*/
#define LDCP(Q,D,G,R,S) ((R)?_F_:((S)?_T_:((G)?((D)?_T_:_F_):((Q)?_T_:_F_))))
#endif
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А вот пример VHDL программы 10-битного счётчика: Я взял "Mapped Logic" из RPT-файла, сгенерированного Xilinx ISE, и пока вручную преобразовал в сишную программу для симуляции: | | | | Code: #include <stdio.h> #include "xemul.h"
int main(int argc, char **argv) { int i,k = 100;
int CLR = _T_; int CEN = _T_; int CLK = _F_; int _OUTPUT0,OUTPUT0 = 0; int _OUTPUT1,OUTPUT1 = 0; int _OUTPUT2,OUTPUT2 = 0; int _OUTPUT3,OUTPUT3 = 0; int _OUTPUT4,OUTPUT4 = 0; int _OUTPUT5,OUTPUT5 = 0; int _OUTPUT6,OUTPUT6 = 0; int _OUTPUT7,OUTPUT7 = 0; int _OUTPUT8,OUTPUT8 = 0; int _OUTPUT9,OUTPUT9 = 0;
if(argc>1) k = atoi(argv[1]);
for(i=0;i<k;i++) {
switch(i%10) { case 0: CLK = _F_; break; case 1: CLK = _F_; break; case 2: CLK = _F_; break; case 3: CLK = _F_; break; case 4: CLK = _R_EDGE; break; case 5: CLK = _T_; break; case 6: CLK = _T_; break; case 7: CLK = _T_; break; case 8: CLK = _T_; break; case 9: CLK = _F_EDGE; break; }
_OUTPUT0 = FTCPE(OUTPUT0,_T_,NOT CLK,NOT CLR,_F_,CEN);
_OUTPUT1 = FTCPE(OUTPUT1,OUTPUT0,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T2 \ (OUTPUT0 AND OUTPUT1)
_OUTPUT2 = FTCPE(OUTPUT2,OUTPUT_T2,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T3 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2)
_OUTPUT3 = FTCPE(OUTPUT3,OUTPUT_T3,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T4 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3)
_OUTPUT4 = FTCPE(OUTPUT4,OUTPUT_T4,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T5 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \ OUTPUT4)
_OUTPUT5 = FTCPE(OUTPUT5,OUTPUT_T5,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T6 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \ OUTPUT4 AND OUTPUT5)
_OUTPUT6 = FTCPE(OUTPUT6,OUTPUT_T6,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T7 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \ OUTPUT4 AND OUTPUT5 AND OUTPUT6)
_OUTPUT7 = FTCPE(OUTPUT7,OUTPUT_T7,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T8 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \ OUTPUT4 AND OUTPUT5 AND OUTPUT6 AND OUTPUT7)
_OUTPUT8 = FTCPE(OUTPUT8,OUTPUT_T8,NOT CLK,NOT CLR,_F_,CEN);
#define OUTPUT_T9 \ (OUTPUT0 AND OUTPUT1 AND OUTPUT2 AND OUTPUT3 AND \ OUTPUT4 AND OUTPUT5 AND OUTPUT6 AND OUTPUT7 AND OUTPUT8)
_OUTPUT9 = FTCPE(OUTPUT9,OUTPUT_T9,NOT CLK,NOT CLR,_F_,CEN);
OUTPUT0 = _OUTPUT0; OUTPUT1 = _OUTPUT1; OUTPUT2 = _OUTPUT2; OUTPUT3 = _OUTPUT3; OUTPUT4 = _OUTPUT4; OUTPUT5 = _OUTPUT5; OUTPUT6 = _OUTPUT6; OUTPUT7 = _OUTPUT7; OUTPUT8 = _OUTPUT8; OUTPUT9 = _OUTPUT9;
printf("%i) %c %c %c (%c) -> %c %c %c %c %c %c %c %c %c %c\n", i, CHR(CLR),CHR(CEN),CHR(CLK),CHR(NOT CLK), CHR(OUTPUT0),CHR(OUTPUT1),CHR(OUTPUT2),CHR(OUTPUT3),CHR(OUTPUT4), CHR(OUTPUT5),CHR(OUTPUT6),CHR(OUTPUT7),CHR(OUTPUT8),CHR(OUTPUT9));
}
return 0; }
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Выхлоп:
Как видим наш счётчик очень зачудительно считает
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03 Dec 2013 21:49 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Чего-то двойной счётчик с горизонтальным и вертикальным сбросом (повторил как сделано в спартановском VGA видео генераторе из интернета):
Генерит глючный код для XC9500 - считает неправильно колонки и не переводит строки | | | | Code: FTCPE_H0: FTCPE port map (H0,'1',NOT CLK,NOT CLR,'0');
FTCPE_H1: FTCPE port map (H1,H1_T,NOT CLK,NOT CLR,'0'); H1_T <= ((NOT H0) OR (NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_H2: FTCPE port map (H2,H2_T,NOT CLK,NOT CLR,'0'); H2_T <= (H0 AND H1);
FTCPE_H3: FTCPE port map (H3,H3_T,NOT CLK,NOT CLR,'0'); H3_T <= (H0 AND H1 AND H2);
FTCPE_H4: FTCPE port map (H4,H4_T,NOT CLK,NOT CLR,'0'); H4_T <= (H0 AND H1 AND H2 AND H3);
FTCPE_H5: FTCPE port map (H5,H5_T,NOT CLK,NOT CLR,'0'); H5_T <= (H0 AND H1 AND H2 AND H3 AND H4);
FTCPE_H6: FTCPE port map (H6,H6_T,NOT CLK,NOT CLR,'0'); H6_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5);
FTCPE_H7: FTCPE port map (H7,H7_T,NOT CLK,NOT CLR,'0'); H7_T <= ((H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6) OR (H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_H8: FTCPE port map (H8,H8_T,NOT CLK,NOT CLR,'0'); H8_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6 AND H7);
FTCPE_H9: FTCPE port map (H9,H9_T,NOT CLK,NOT CLR,'0'); H9_T <= ((H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6 AND H7 AND H8) OR (H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
SYNC <= '1';
FTCPE_V0: FTCPE port map (V0,V0_T,NOT CLK,NOT CLR,'0'); V0_T <= ((NOT V4 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (NOT V5 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (NOT V8 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V7 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V9 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V0 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V1 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V2 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (NOT V3 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9) OR (V6 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_V1: FTCPE port map (V1,V1_T,NOT CLK,NOT CLR,'0'); V1_T <= (V0 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);
FTCPE_V2: FTCPE port map (V2,V2_T,NOT CLK,NOT CLR,'0'); V2_T <= (V0 AND V1 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);
FTCPE_V3: FTCPE port map (V3,V3_T,NOT CLK,NOT CLR,'0'); V3_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND NOT V9) OR (V0 AND V1 AND V2 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_V4: FTCPE port map (V4,V4_T,NOT CLK,NOT CLR,'0'); V4_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND NOT V9) OR (V0 AND V1 AND V2 AND V3 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_V5: FTCPE port map (V5,V5_T,NOT CLK,NOT CLR,'0'); V5_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND NOT V9) OR (V0 AND V1 AND V2 AND V3 AND V4 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_V6: FTCPE port map (V6,V6_T,NOT CLK,NOT CLR,'0'); V6_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);
FTCPE_V7: FTCPE port map (V7,V7_T,NOT CLK,NOT CLR,'0'); V7_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);
FTCPE_V8: FTCPE port map (V8,V8_T,NOT CLK,NOT CLR,'0'); V8_T <= ((NOT V0 AND NOT V1 AND NOT V2 AND V3 AND V4 AND V5 AND NOT V6 AND NOT V7 AND V8 AND NOT V9) OR (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9));
FTCPE_V9: FTCPE port map (V9,V9_T,NOT CLK,NOT CLR,'0'); V9_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7 AND V8 AND H0 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H7 AND NOT H8 AND H9);
VID <= '1';
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);
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Чтоли заводить сбросы через наружу?...
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04 Dec 2013 06:13 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Вывел сбросы HCLR и VCLR через триггеры и завёл обратно без клока - теперь вроде работает:
Вот во что это теперь раскладывается: | | | | Code: ********** Mapped Logic **********
FTCPE_H0: FTCPE port map (H0,'1',NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
FTCPE_H1: FTCPE port map (H1,H0,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR);
FTCPE_H2: FTCPE port map (H2,H2_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H2_T <= (H0 AND H1);
FTCPE_H3: FTCPE port map (H3,H3_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H3_T <= (H0 AND H1 AND H2);
FTCPE_H4: FTCPE port map (H4,H4_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H4_T <= (H0 AND H1 AND H2 AND H3);
FTCPE_H5: FTCPE port map (H5,H5_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H5_T <= (H0 AND H1 AND H2 AND H3 AND H4);
FTCPE_H6: FTCPE port map (H6,H6_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H6_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5);
FTCPE_H7: FTCPE port map (H7,H7_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H7_T <= (H0 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);
FTCPE_H8: FTCPE port map (H8,H8_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H8_T <= (H0 AND H7 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);
FTCPE_H9: FTCPE port map (H9,H9_T,NOT CLK,NOT HTMP(9)/HTMP(9)_RSTF__$INT,'0',VCLR); H9_T <= (H0 AND H7 AND H8 AND H1 AND H2 AND H3 AND H4 AND H5 AND H6);
FDCPE_HCLR: FDCPE port map (HCLR,'0',NOT CLK,'0',NOT HTMP(9)/HTMP(9)_RSTF__$INT,HCLR_CE); HCLR_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND VCLR);
HTMP(9)/HTMP(9)_RSTF__$INT <= (HCLR AND CLR);
FDCPE_SYNC: FDCPE port map (SYNC,SYNC_D,NOT CLK,'0',NOT SYNC_OBUF/SYNC_OBUF_SETF__$INT); SYNC_D <= ((H7 AND H8 AND H3 AND H4 AND H6 AND NOT H9) OR (NOT V1 AND NOT V2 AND V3 AND V8 AND V4 AND NOT V5 AND NOT V6 AND NOT V7 AND NOT V9) OR (V0 AND V1 AND V2 AND NOT V3 AND V8 AND V4 AND NOT V5 AND NOT V6 AND NOT V7 AND NOT V9) OR (H7 AND H8 AND H5 AND H6 AND NOT H9) OR (H0 AND H7 AND H8 AND H4 AND H6 AND NOT H9) OR (H7 AND H8 AND H1 AND H4 AND H6 AND NOT H9) OR (H7 AND H8 AND H2 AND H4 AND H6 AND NOT H9));
SYNC_OBUF/SYNC_OBUF_SETF__$INT <= (VCLR AND HCLR AND CLR);
FTCPE_V0: FTCPE port map (V0,'1',NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V0_CE); V0_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V1: FTCPE port map (V1,V0,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V1_CE); V1_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V2: FTCPE port map (V2,V2_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V2_CE); V2_T <= (V0 AND V1); V2_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V3: FTCPE port map (V3,V3_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V3_CE); V3_T <= (V0 AND V1 AND V2); V3_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V4: FTCPE port map (V4,V4_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V4_CE); V4_T <= (V0 AND V1 AND V2 AND V3); V4_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V5: FTCPE port map (V5,V5_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V5_CE); V5_T <= (V0 AND V1 AND V2 AND V3 AND V4); V5_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V6: FTCPE port map (V6,V6_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V6_CE); V6_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5); V6_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V7: FTCPE port map (V7,V7_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V7_CE); V7_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6); V7_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V8: FTCPE port map (V8,V8_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V8_CE); V8_T <= (V0 AND V1 AND V2 AND V3 AND V4 AND V5 AND V6 AND V7); V8_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FTCPE_V9: FTCPE port map (V9,V9_T,NOT CLK,NOT VTMP(9)/VTMP(9)_RSTF__$INT,'0',V9_CE); V9_T <= (V0 AND V1 AND V2 AND V3 AND V8 AND V4 AND V5 AND V6 AND V7); V9_CE <= (NOT H0 AND H7 AND NOT H8 AND NOT H1 AND NOT H2 AND NOT H3 AND NOT H4 AND NOT H5 AND NOT H6 AND H9 AND HCLR);
FDCPE_VCLR: FDCPE port map (VCLR,'0',NOT CLK,'0',NOT VTMP(9)/VTMP(9)_RSTF__$INT,VCLR_CE); VCLR_CE <= (V0 AND V1 AND V2 AND NOT V3 AND V8 AND V4 AND V5 AND NOT V6 AND NOT V7 AND NOT V9 AND HCLR);
FDCPE_VID: FDCPE port map (VID,VID_D,NOT CLK,'0',NOT VID_OBUF/VID_OBUF_SETF__$INT); VID_D <= ((NOT H7 AND NOT H9 AND NOT V8 AND NOT V9) OR (NOT H8 AND NOT H9 AND NOT V8 AND NOT V9));
VID_OBUF/VID_OBUF_SETF__$INT <= (VCLR AND HCLR AND CLR);
VTMP(9)/VTMP(9)_RSTF__$INT <= (VCLR AND CLR);
Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE);
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P.S. Почему-то SYNC получился инвертированным - глюкодром какой-то
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04 Dec 2013 17:00 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Правильный SYNC удалось получить только вот так:
P.S. т.е. получается, что условие со сравнением чисел работает только если после then стоит присвоение '1', а в случе '0' получается инвертированный вариант... P.P.S. это точно косяк Xilinx ISE, т.к. я ещё раз поменял местами '0' и '1' в условии if VTMP>278 and VTMP<282 then и получил вот такую разницу в репортах: как видим она сугубо косметическая... P.P.S. Однако JED-файлы отличаются более разумно: В этом случае похоже на косяк RPT-репорта, который не инвертирует некоторые выходы в "Mapped Logic"... P.P.P.S. И точно:
Значит RPT-файлу нельзя доверять...
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05 Dec 2013 04:58 |
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Shaos
Admin
Joined: 08 Jan 2003 23:22 Posts: 22879 Location: Silicon Valley
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Научился запускать симулятор - первое что надо делать это добавить новый исходник "VHDL Test Bench", в котором будут описаны входные воздействия на VHDL - после этого будет запускаться симулятор ISim...
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12 Dec 2013 23:34 |
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